Patent US4804867A successfully refreshed from Google Patents.
US4804867A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three-state complementary MOS integrated circuit
Assignee: Mitsubishi Electric Corp
•
Filing: 1987-11-10
•
Granted: 1989-02-14
•
Expires: 2007-11-10
Abstract
Abstract In a three-state complementary MOS integrated circuit having an output circuit comprising a P-channel MOS transistor and an N-channel MOS transistor, part of a pre-output stage circuit between the gate inputs of the P-channel MOS transistor and the N-channel MOS transistor of the output circuit comprises a parallel circuit of a first series circuit and a second series circuit, each of the first series circuits comprising a P-channel MOS transistor to which the control signal is applied and an N-channel MOS transistor to which the in inverted control signal is applied. When the control signal and the inverted control signal are at the same potential, either the P-channel MOS transistors or the N-channel MOS transistors of the parallel circuit are off. Accordingly totempole current through the pre-output stage circuit is avoided.
Inventors
- 👤 Takenori Okitaka
- 👤 Yukio Miyazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:56
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0008; H03K19/0013; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
284 words
A three-state complementary MOS integrated circuit comprising an output circuit comprising a P-channel MOS transistor and an N-channel MOS transistor that are connected in series between a power supply and a ground, and a pre-output stage circuit responsive to a control signal, an inverted control signal and an input signal for driving the output circuit, wherein the pre-output stage circuit comprises a first parallel circuit of a P-channel MOS transistor having a gate connected to receive the input signal and a P-channel MOS transistor have a gate connected to receive the inverted control signal, a second parallel circuit of a first series circuit and a second series circuit, the first series circuit comprising a series connection of a P-channel MOS transistor having a gate connected to receive the control signal and an N-channel MOS transistor having a gate connected to receive the inverted control signal, and the second series circuit comprising a series connection of a P-channel MOS transistor having a gate connected to receive the control signal and an N-channel MOS transistor having a gate connected to receive the inverted control signal, and a third parallel circuit of an N-channel MOS transistor having a gate connected to receive the control signal and an N-channel MOS transistor having a gate connected to receive the input signal, wherein the first, second and third parallel circuit are series-connected in the stated order between the power supply and the ground, the junction between the first and second parallel circuits is connected to the gate of the P-channel MOS transistor of the output circuit, and the junction between the second and third parallel circuits is connected to the gate of the N-channel MOS transistor of the output circuit.
Claim 2
Dependent Claim
284 words
A three-state complementary MOS integrated circuit comprising an output circuit comprising a P-channel MOS transistor and an N-channel MOS transistor that are connected in series between a power supply and a ground, and a pre-output stage circuit responsive to a control signal, an inverted control signal and an input signal for driving the output circuit, wherein the pre-output stage circuit comprises a first parallel circuit of a P-channel MOS transistor having a gate connected to receive the input signal and a P-channel MOS transistor have a gate connected to receive the inverted control signal, a second parallel circuit of a first series circuit and a second series circuit, the first series circuit comprising a series connection of a P-channel MOS transistor having a gate connected to receive the control signal and an N-channel MOS transistor having a gate connected to receive the inverted control signal, and the second series circuit comprising a series connection of a P-channel MOS transistor having a gate connected to receive the control signal and an N-channel MOS transistor having a gate connected to receive the inverted control signal, and a third parallel circuit of an N-channel MOS transistor having a gate connected to receive the control signal and an N-channel MOS transistor having a gate connected to receive the input signal, wherein the first, second and third parallel circuit are series-connected in the stated order between the power supply and the ground, the junction between the first and second parallel circuits is connected to the gate of the P-channel MOS transistor of the output circuit, and the junction between the second and third parallel circuits is connected to the gate of the N-channel MOS transistor of the output circuit.
Claim 3
Dependent Claim
67 words
A three-state complementary MOS integrated circuit according to claim 1, wherein the junction between the P-channel MOS transistor and the N-channel MOS transistor of the output circuit constitutes the output terminal of the three-state complementary MOS integrated circuit, the P-channel MOS transistor being connected between the output terminal and the power supply terminal and the N-channel MOS transistor being connected between the output terminal and the ground.
Claim 4
Dependent Claim
54 words
A three-state complementary MOS integrated circuit according to claim 1, wherein the first parallel circuit is connected between the gate of the P-channel transistor of the output circuit and the power supply terminal and the third parallel circuit is connected between the gate of the N-channel transistor of the output circuit and the ground.
Claim 5
Dependent Claim
23 words
A three-state complementary MOS circuit according to claim 1, wherein the power supply terminal has a positive potential with respect to the ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |