Patent US4803566A successfully refreshed from Google Patents.
US4803566A
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Digital time base correction using a reference bit
Assignee: Eastman Kodak Co
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Filing: 1983-08-01
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Granted: 1989-02-07
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Expires: 2003-08-01
Abstract
Abstract In a multi-channel device for the processing of digital data bytes comprised of parallel arrangements of data bits, the invention calls for recognition of the fact that--irrespective of skew and other interchannel variations in the processing of such data bits--the median-occurring bit of each successive data byte constitutes a good representative of the time of occurrence of the byte in question. By suitably buffering the bits of successive data bytes, a "median clock" that is slaved to the aforenoted "median-occurring" bits may be used to clock data bytes--devoid of inter-channel timing errors--out of the apparatus used for the indicated buffering operation.
Inventors
- 👤 Elwyn R. Berlekamp
- 👤 James A. Bixby
- 👤 James U. Lemke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:05
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/20
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
130 words
Apparatus for assuring time coherence among data bits in a multi-channel bit-processing system, groupings of said bits comprising respective bytes, and said bytes occurring in a time sequence, said apparatus comprising: (a) respective clockable multi-bit buffer means for receiving the bits of said sequenced bytes, (b) means for detecting the occurrence of a reference bit for, and from within, each of a plurality of said bytes, and (c) means responsive to reference bit occurrences for producing a clock having a frequency corresponding thereto, said clock being applied to each of said buffer means for clocking therefrom data bits which are essentially devoid of time incoherence thereamong, said means for detecting the occurrence of a reference bit being means for detecting the median-occuring bit of each of said plurality of bytes.
Claim 2
Dependent Claim
130 words
Apparatus for assuring time coherence among data bits in a multi-channel bit-processing system, groupings of said bits comprising respective bytes, and said bytes occurring in a time sequence, said apparatus comprising: (a) respective clockable multi-bit buffer means for receiving the bits of said sequenced bytes, (b) means for detecting the occurrence of a reference bit for, and from within, each of a plurality of said bytes, and (c) means responsive to reference bit occurrences for producing a clock having a frequency corresponding thereto, said clock being applied to each of said buffer means for clocking therefrom data bits which are essentially devoid of time incoherence thereamong, said means for detecting the occurrence of a reference bit being means for detecting the median-occuring bit of each of said plurality of bytes.
Claim 3
Dependent Claim
51 words
Apparatus of claim 1 wherein said buffer means are respectively comprised of first and second serially connected parts, and wherein said means for detecting said median-occuring bits is means for repeatedly detecting the occurrence of approximately a given number of buffer means first parts which are fully loaded with data bits.
Claim 4
Dependent Claim
78 words
Apparatus of claim 2 (a) wherein said buffer means first and second parts are asynchronous two-port memories of the type which respectively produce flag signal voltages when fully loaded with data bits, and (b) wherein said apparatus further comprises (1) means for algebraically summing said flag signal voltages and (2) means responsive to said sum signal voltage for clocking said data bits from said buffer means at a rate that is in proportion to said sum signal voltage.
Claim 5
Dependent Claim
19 words
The apparatus of claim 3 wherein said means responsive to said sum signal voltage is a voltage controlled oscillator.
Claim 6
Dependent Claim
43 words
The apparatus of claim 4 further comprising means for nonlinearly modifying said sum signal voltage before its application to said voltage controlled oscillator., whereby the output frequency thereof nonlinearly increases whenever said sum signal voltage departs from a quiescent value or range thereof.
Claim 7
Dependent Claim
44 words
The apparatus of claim 3 further comprising means for nonlinearly modifying said sum signal voltage before its application to said means for clocking, whereby the rate of said clocking nonlinearly increases whenever said sum signal voltages departs from a quiescent value or range thereof.
Claim 8
Dependent Claim
126 words
In multi-channel apparatus for the parallel processing of the bits of successive bytes, the improvement of time base correction means for removing time incoherence among said bits, said time base correction means comprising (a) data bit buffering means in each of said channels for respectively receiving the bits of said bytes at respective bit rates, (b) means for detecting a reference bit for, and from within, each of said successive bytes, and (c) means responsive to said means for detecting for clocking data bits from each of said data bits buffering means, thereby to form therefrom bytes of time coherent bits, said means for detecting a reference bit for each of said successive bytes being means for detecting the median-occurring bit of each of said bytes.
Claim 9
Dependent Claim
126 words
In multi-channel apparatus for the parallel processing of the bits of successive bytes, the improvement of time base correction means for removing time incoherence among said bits, said time base correction means comprising (a) data bit buffering means in each of said channels for respectively receiving the bits of said bytes at respective bit rates, (b) means for detecting a reference bit for, and from within, each of said successive bytes, and (c) means responsive to said means for detecting for clocking data bits from each of said data bits buffering means, thereby to form therefrom bytes of time coherent bits, said means for detecting a reference bit for each of said successive bytes being means for detecting the median-occurring bit of each of said bytes.
Claim 10
Dependent Claim
51 words
The apparatus of claim 7 wherein (a) said data bit buffering means are respectively comprised of first and second serially connected parts and (b) said means for detecting said median occurring bits is means for producing a signal whenever there occurs a given number of fully loaded buffering means first parts.
Claim 11
Dependent Claim
85 words
The apparatus of claim 8 (a) wherein the firs and second parts of said data bit buffering means are asychronous two-port memories of the type which respectively produce flag signal voltages when fully loaded with data bits, and (b) said time base correction means further comprises (1) means for adding together said flag voltages to form a sum signal voltage and (2) means responsive to said sum signal voltage for clocking said data bits out of all said buffering means at a rate proportional thereto.
Claim 12
Dependent Claim
19 words
The apparatus of claim 9 wherein said means responsive to said sum signal voltage is a voltage controlled oscillator.
Claim 13
Dependent Claim
43 words
The apparatus of claim 10 further comprising means for nonlinearly modifying said sum signal voltage before its application to said voltage controlled oscillator, whereby the output frequency thereof nonlinearly increases whenever said sum signal voltage departs from a quiescent value or range thereof.
Claim 14
Dependent Claim
44 words
The apparatus of claim 9 further comprising means for nonlinearly modifying said sum signal voltage before its application to said means for clocking, whereby the rate of said clocking nonlinearly increases whenever said sum signal voltage departs from a quiescent value or range thereof.
Claim 15
Dependent Claim
85 words
Multi-channel apparatus for removing channel-to-channel asynchronism among the parallel bits of bytes in a succession of bytes comprising (a) means for producing a clock signal corresponding to the median bit of and from within each said byte (b) clockable multi-bit buffer means in each said channel for receiving at random times respective bits of said bytes, and (c) means for applying said median bit clock signal to all said buffer means to clock bytes therefrom which are composed of bits having the same time frame.
Claim 16
Dependent Claim
85 words
Multi-channel apparatus for removing channel-to-channel asynchronism among the parallel bits of bytes in a succession of bytes comprising (a) means for producing a clock signal corresponding to the median bit of and from within each said byte (b) clockable multi-bit buffer means in each said channel for receiving at random times respective bits of said bytes, and (c) means for applying said median bit clock signal to all said buffer means to clock bytes therefrom which are composed of bits having the same time frame.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |