← Back to Patent Explorer
US4801824A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrable buffer circuit for voltage level conversion having clamping means

Assignee: Infineon Technologies AG
•
Filing: 1987-07-21
•
Granted: 1989-01-31
•
Expires: 2007-07-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A signal voltage (E) based upon a supply voltage must be converted to a signal voltage (A) with ground reference so as to enable further processing in a logic circuit. A simple level converter comprises a series connection of a MOSFET (T1) connected to the supply voltage; the MOSFET also comprises a resistor (T2). The source terminal of the MOSFET (T1) is located at the potential of the supply voltage. The voltage to be converted is applied between the gate terminal and the source terminal, and the converted voltage occurs at the resistor (T2). The two voltages are each limited by one Zener diode (D2, D1).

Inventors

  • 👤 Christine Fellinger
  • 👤 Josef Einzinger
  • 👤 Ludwid Leipold
  • 👤 Jenoe Tihanyi
  • 👤 Roland Weber

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 23:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K19/09482; H03K19/0175; H03K19/0185; H03K19/018507

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 163 words
A circuit arrangement for converting a first signal voltage, referenced to a voltage supply potential, into a second signal voltage referenced to ground potential, the arrangement comprising: (a) a MOSFET and at least one resistor serially connected between a first and a second terminal; (b) the MOSFET having a source terminal connected to the first terminal; (c) at least one diode is connected in the forward direction of the flow of current between the first terminal and the source terminal of the MOSFET; (d) the MOSFET having a gate terminal connected to a third terminal; (e) a first Zener diode is connected between the first terminal and the third terminals for limiting the first signal voltage; (f) a fourth terminal is connected to one terminal of the resistor while the other terminal of the resistor is connected to the second terminal; and (g) a second Zener diode is connected between the second terminal and the fourth terminal for limiting the second signal voltage.
Claim 2
Dependent Claim 163 words
A circuit arrangement for converting a first signal voltage, referenced to a voltage supply potential, into a second signal voltage referenced to ground potential, the arrangement comprising: (a) a MOSFET and at least one resistor serially connected between a first and a second terminal; (b) the MOSFET having a source terminal connected to the first terminal; (c) at least one diode is connected in the forward direction of the flow of current between the first terminal and the source terminal of the MOSFET; (d) the MOSFET having a gate terminal connected to a third terminal; (e) a first Zener diode is connected between the first terminal and the third terminals for limiting the first signal voltage; (f) a fourth terminal is connected to one terminal of the resistor while the other terminal of the resistor is connected to the second terminal; and (g) a second Zener diode is connected between the second terminal and the fourth terminal for limiting the second signal voltage.
Claim 3
Dependent Claim 36 words
A circuit arrangement according to claim 1, comprising a further resistor connected between a drain terminal of the MOSFET and the one terminal of the resistor while the other terminal is connected to the second terminal.
Claim 4
Dependent Claim 26 words
A circuit arrangement as defined in claim 1, wherein the resistors each comprise a depletion MOSFET wherein its source terminal and its gate terminal are interconnected.
Claim 5
Dependent Claim 26 words
A circuit arrangement as defined in claim 3, wherein the resistors each comprise a depletion MOSFET wherein its source terminal and its gate terminal are interconnected.

References Cited (Backward Citations)

US3731206A Cited
US3746893A Cited
US3947727A Cited
US4697110A Cited
US4728821A Cited
US4723082A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-01-31 1992-08-01 1993-01-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-01-31 1996-08-01 1997-01-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-01-31 2000-08-01 2001-01-31 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag