Patent US4800517A successfully refreshed from Google Patents.
US4800517A
Expired / Lapsed
US
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Word-sliced signal processor
Assignee: RPX Corp
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Filing: 1986-07-30
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Granted: 1989-01-24
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Expires: 2006-07-30
Abstract
Abstract Method and apparatus for processing digital signals represented as binary words, employing a portion of each word (a "slice") to afford appropriate accuracy. Particularly suited to medium- to high-speed telecommunications applications. In an exemplary transversal filtering operation application, only the high-order slice of the updated coefficient need be used to perform the filtering and yet provide adequate precision. Description of an architecture of a word-slice digital signal processor and applications to adaptive equalization and automatic gain control are provided.
Inventors
- 👤 Safdar M. Asghar
- 👤 Hwa-Sheng Pyi
- 👤 Dermot Dunnion
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:32
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5324; G06F15/00; G06F15/76; G06F15/78; G06F15/7896
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
363 words
A digital signal processor connected to a bus conducting plural-bit data words each word consisting of a predetermined number of "slices" comprising: first means connected to said bus for receiving a first word slice, shifting said slice a selectable number of bits and storing the resulting slice; second means connected to said bus for receiving a second word slice, shifting said slice a selectable number of bits and storing the resulting slice; multiplier means responsive to said slices stored in said first and second shifting means, for generating a two-slice product of said first and second slices; first multiplexer means connected to said first shifting means and to said multiplier means for selectably generating at a set of output terminals either said first slice padded with a low-order slice of zeros or said two-slice products; third means connected to said first multiplexer means output terminals for receiving said two-slices generated thereat, shifting said two-slices a selectable number of bits and storing the resulting two-slices; second multiplexer means having a first set of input terminals connected to said third shifting means and a second set of input terminals for selectably generating at a set of output terminals either the two-slices received at said first set of input terminals or the two-slices received at said second set of input terminals; arithmetic logic unit means having a first set of input terminals connected to said output terminals of said second multiplexer means and a second set of input terminals for generating a selectable two slice combinatorial result of the two-slice operands received at said first and second set of input terminals, and for accumulating and storing said selected combinatorial result; said accumulated result received at said second set of input terminals of said arithmetic logic unit and said second multiplexer means; and third multiplexer means having a first set of input terminals receiving a first slice of said two-slice accumulated result and a second set of input terminals receiving a second slice of said two-slice accumulated result and a set of output terminals connected to said data bus for selectably generating at said output terminals said first or said second slice applied to said input terminals.
Claim 2
Dependent Claim
363 words
A digital signal processor connected to a bus conducting plural-bit data words each word consisting of a predetermined number of "slices" comprising: first means connected to said bus for receiving a first word slice, shifting said slice a selectable number of bits and storing the resulting slice; second means connected to said bus for receiving a second word slice, shifting said slice a selectable number of bits and storing the resulting slice; multiplier means responsive to said slices stored in said first and second shifting means, for generating a two-slice product of said first and second slices; first multiplexer means connected to said first shifting means and to said multiplier means for selectably generating at a set of output terminals either said first slice padded with a low-order slice of zeros or said two-slice products; third means connected to said first multiplexer means output terminals for receiving said two-slices generated thereat, shifting said two-slices a selectable number of bits and storing the resulting two-slices; second multiplexer means having a first set of input terminals connected to said third shifting means and a second set of input terminals for selectably generating at a set of output terminals either the two-slices received at said first set of input terminals or the two-slices received at said second set of input terminals; arithmetic logic unit means having a first set of input terminals connected to said output terminals of said second multiplexer means and a second set of input terminals for generating a selectable two slice combinatorial result of the two-slice operands received at said first and second set of input terminals, and for accumulating and storing said selected combinatorial result; said accumulated result received at said second set of input terminals of said arithmetic logic unit and said second multiplexer means; and third multiplexer means having a first set of input terminals receiving a first slice of said two-slice accumulated result and a second set of input terminals receiving a second slice of said two-slice accumulated result and a set of output terminals connected to said data bus for selectably generating at said output terminals said first or said second slice applied to said input terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-24 | 1992-07-25 | 1993-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-24 | 1996-07-25 | 1997-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-24 | 2000-07-25 | 2001-01-24 | $7700.00 | Window Closed / Lapsed |