Apparatus and method for capacitor coupled complementary buffering

Claim 2

A semiconductor buffer circuit responsive to a digital input signal for driving a capacitive load to one of two binary states, comprising: first transistor means having a first, second, and control electrode, the first electrode coupled to a first reference potential and the second electrode to be coupled to the capacitive load, for charging the capacitive load by current from the first reference potential through the first transistor means at times when the input signal is changing to a high level; second transistor means having a first, second, and control electrode, the first electrode coupled to a second reference potential lower than the first reference potential and the second electrode to be coupled to the capacitive load, for discharging the capacitive load by current to the second reference potential through the second transistor means at times when the input signal is changing to a low level; first coupling means for coupling the digital input signal to the control electrode of the first transistor means, for applying a voltage to the control electrode that increases the current between the first and second electrodes of the first transistor means at times when the input signal is changing to a high level, and decreases the current at times when the input signal is changing to a low level; and second coupling means for capacitively coupling the digital input signal to the control electrode of the second transistor means, for applying a voltage to the control electrode that decreases the current between the first and second electrodes of the second transistor means at times when the input signal is changing to a high level, and increases the current at times when the input signal is changing to a low level.

Claim 3

A buffer circuit in accordance with claim 1, in which the second coupling means comprises: a capacitor coupled to the control electrode of the second transistor means; and means for applying the complement of the digital input signal to said capacitor.

Claim 4

A buffer circuit in accordance with claim 2, in which the first and second transistor means comprise field effect transistors.

Claim 5

A buffer circuit in accordance with claim 2, in which the first and second transistor means comprise junction field effect transistors.

Claim 6

A buffer circuit in accordance with claim 2, in which the first and second transistor means comprise bipolar transistors.

Claim 7

A buffer circuit in accordance with claim 2, and further comprising: transistor control coupling means for coupling the control electrode of the second transistor means to the second reference potential, for applying a voltage to said control electrode that maintains the current between the first and second electrodes of the second transistor means at a predetermined value at times when the input signal is not changing.

Claim 8

A buffer circuit in accordance with claim 6, wherein the second transistor means is a depletion mode transistor, in which the transistor control coupling means comprises: a resistor having a selected resistance value such that the voltage drop across the resistor is substantially equal to zero except at times when the input signal is changing.

Claim 9

A buffer circuit in accordance with claim 2, and further comprising: diode means coupling the control electrode of the second transistor means to the second reference potential and operative to clamp the voltage applied to said control electrode.

Claim 10

A buffer circuit in accordance with claim 2, in which the buffer circuit drives a memory word line.

Claim 11

A buffer circuit in accordance with claim 2, in which the semiconductor buffer circuit is comprised of gallium arsenide.

Claim 12

A buffer circuit in accordance with claim 2, in which the semiconductor buffer circuit is comprised of silicon.

Claim 13

A buffer circuit in accordance with claim 3, in which the transistors comprise depletion mode transistors.

Claim 16

A method for driving a capacitive load in accordance with claim 13, and further comprising the step of: clamping the maximum amplitude of the signal coupled to the control electrode of the second transistor.

Claim 17

A method for driving a capacitive load in accordance with claim 13, in which: the step of capacitively coupling the complement of the digital input signal for decreasing the discharging current to the second reference potential at times when the input signal is changing from a low to a high level is operative to cut off the second transistor.

Claim 18

A method for driving a capacitive load in accordance with claim 13, in which: the step of coupling the digital input signal for decreasing the charging current from the first reference potential at times when the input signal is changing from a high to a low level is operative to cut off the first transistor.

Claim 19

A buffer circuit responsive to a digital input signal for driving a memory word line, comprising: first transistor means having a first, second, and control electrode, the first electrode coupled to a first reference potential and the second electrode to be coupled to the memory word line, for charging the memory word line by current from the first reference potential through the first transistor means when the input signal is changing to a high level; second transistor means having a first, second, and control electrode, the first electrode coupled to a second reference potential lower than the first reference potential and the second electrode to be coupled to the memory word line, for discharging the memory word line by current to the second reference potential through the second transistor means when the input signal is changing to a low level; first coupling means for coupling the digital input signal to the control electrode of the first transistor means, for applying a voltage to the control electrode that increases the current between the first and second electrodes of the first transistor means at times when the input signal is changing to a high level and decreases the current at times when the input signal is changing to a low level; and second coupling means for capacitively coupling the complement of the digital input signal to the control electrode of the second transistor means, for applying a voltage to the control electrode that decreases the current between the first and second electrodes of the second transistor means at times when the input signal is changing to a high level and increases the current at times when the input signal is changing to a low level.

Claim 20

A buffer circuit responsive to a digital input signal for driving a memory word line, comprising: first transistor means having a first, second, and control electrode, the first electrode coupled to a first reference potential and the second electrode to be coupled to the memory word line, for charging the memory word line by current from the first reference potential through the first transistor means when the input signal is changing to a high level; second transistor means having a first, second, and control electrode, the first electrode coupled to a second reference potential lower than the first reference potential and the second electrode to be coupled to the memory word line, for discharging the memory word line by current to the second reference potential through the second transistor means when the input signal is changing to a low level; first coupling means for coupling the digital input signal to the control electrode of the first transistor means, for applying a voltage to the control electrode that increases the current between the first and second electrodes of the first transistor means at times when the input signal is changing to a high level and decreases the current at times when the input signal is changing to a low level; and second coupling means for capacitively coupling the complement of the digital input signal to the control electrode of the second transistor means, for applying a voltage to the control electrode that decreases the current between the first and second electrodes of the second transistor means at times when the input signal is changing to a high level and increases the current at times when the input signal is changing to a low level.

Claim 21

A buffer circuit in accordance with claim 17, in which the second coupling means further comprises: third transistor means having a first, second, and control electrode, the first electrode operatively coupled to raise the voltage applied to the control electrode of the second transistor means at times when the input signal is changing to a low level and the second electrode coupled to the control electrode of the second transistor means; fourth transistor means having a first, second, and control electrode, the first electrode coupled to a third reference potential lower than the second reference potential and the second electrode coupled to the control electrode of the second transistor means; third coupling means for capacitively coupling the digital input signal to the control electrode of the fourth transistor means, for applying a voltage to said control electrode that increases the current between the first and second electrodes of the fourth transistor means at times when the input signal is changing to a high level and decreases the current at times when the input signal is changing to a low level, wherein the increased current to the third reference potential at times when the input signal is changing to a high level lowers the voltage applied to the control electrode of the second transistor means and thereby decreases the current between the first and second electrodes of the second transistor means; and fourth coupling means for capacitively coupling the complement of the digital input signal to the control electrode of the third transistor means, for applying a voltage to said control electrode that increases the current between the first and second electrodes of the third transistor means at times when the input signal is changing to a low level and decreases the current at times when the input signal is changing to a high level, wherein the increased current into the first electrode of the third transistor means at times when the input signal is changing to a low level raises the voltage applied to the control electrode of the second transistor means and thereby increases the current between the first and second electrodes of the second transistor means; wherein the current discharging the memory word line increases at times when the input signal is changing to a low level and decreases at times when the input signal is changing to a high level.

Claim 22

A buffer circuit in accordance with claim 18, and further comprising: first discharge resistance means for coupling the control electrode of the third transistor means to the second reference potential; and second discharge resistance means for coupling the control electrode of the fourth transistor means to the third reference potential.

Claim 23

A buffer circuit in accordance with claim 18, and further comprising: first diode means coupling the control electrode of the third transistor means to the second reference potential for clamping the voltage applied to said control electrode.

Claim 24

A buffer circuit in accordance with claim 18, and further comprising: diode means coupling the control electrode of the fourth transistor means to the third reference potential for clamping the voltage applied to said control electrode.

Claim 25

A buffer circuit in accordance with claim 18, in which the buffer circuit is comprised of gallium arsenide.

Claim 26

A buffer circuit in accordance with claim 18, in which the transistor means comprise field effect transistors.

Claim 27

A buffer circuit in accordance with claim 23, in which the transistor means comprise depletion mode transistors.

Claim 28

A buffer circuit in accordance with claim 23, in which a channel in each of the third and fourth transistor means is thinner than a channel in each of the first and second transistor means.

Claim 29

A buffer circuit in accordance with claim 17, in which the second coupling means further comprises: third transistor means having a first, second, and control electrode, the first electrode to be coupled to the memory word line and the second electrode coupled to the control electrode of the second transistor means; fourth transistor means having a first, second, and control electrode, the first electrode coupled to a third reference potential lower than the second reference potential and the second electrode coupled to the control electrode of the second transistor means; third coupling means for capacitively coupling the digital input signal to the control electrode of the fourth transistor means, for applying a voltage to said control electrode that increases the current between the first and second electrodes of the fourth transistor means at times when the input signal is changing to a high level and decreases the current at times when the input signal is changing to a low level, wherein the increased current to the third reference potential at times when the input signal is changing to a high level lowers the voltage applied to the control electrode of the second transistor means and thereby decreases the current between the first and second electrodes of the second transistor means; and fourth coupling means for capacitively coupling the complement of the digital input signal to the control electrode of the third transistor means, for applying a voltage to said control electrode that increases the current between the first and second electrodes of the third transistor means at times when the input signal is changing to a low level and decreases the current at times when the input signal is changing to a high level, wherein the increased current from the memory word line at times when the input signal is changing to a low level raises the voltage applied to the control electrode of the second transistor means and thereby increases the current between the first and second electrodes of the second transistor means, and discharges the memory word line through the third transistor means; wherein the current discharging the memory word line through the second and third transistor means increases at times when the input signal is changing to a low level and decreases at times when the input signal is changing to a high level.