Complementary FET pulse control circuit

Claim 2

A pulse control circuit comprising: an input terminal supplied with a pulse signal; a first FET put into the conductive state in response to said pulse signal; a first time constant circuit charged when said first FET is put in the conductive state; a second FET put into the conductive state with the charging voltage of said first time constant circuit; a second time constant circuit discharging the charged electricity in said first time constant circuit when said second FET is put in the conductive state; an output terminal to deliver an output signal having a wave form in accordance with the time constants of said first and second time constant circuits including first and second DC power sources of different polarity, said first and second FETs connected in series with said first and second DC power sources and said first and second time constant circuits being connected between said first and second FETs, wherein said first and second FETs have drains, sources and gates, said sources being connected to said first and second time constant circuits respectively, and said gates being connected to a biasing circuit including a constant current circuit connected between said first and second DC power sources and a resistor connected in series with said constant current circuit.

Claim 3

A pulse control circuit accordng to claim 1, wherein one end of said resistor connected to said constant current circuit is connected to the gate of said first FET and another end of said resistor is connected to the gate of said second FET, said resistor having a movable contact connected to said input terminal.

Claim 4

A pulse control circuit according to claim 1, wherein said first and second FETs are of the junction-type exhibiting triode-type dynamic characteristics, having polarities opposite to each other, respectively.

Claim 5

A pulse control circuit comprising: an input terminal supplied with a pulse signal; a first FET put into the conductive state in response to said pulse signal; a first time constant circuit charged when said first FET is put in the conductive state; a second FET put into the conductive state with the charging voltage of said first time constant circuit; a second time constant circuit discharging the charged electricity in said first time constant circuit when said second FET is put in the conductive state; an output terminal to deliver an output signal having a wave form in accordance with the time constants of said first and second time constant circuits, wherein said first and second FETs have polarities opposite to each other, drains, sources and gates, first and second DC power sources, the drain of said first FET is connected to said first DC power source, the drain of said second FET is connected to said second DC power source which has a polarity opposite to that of said first DC power source, and the sources of said first and second FETs connected to said first and second time constant circuits, respectively, and a constant current circuit connected to the gates of said first and second FETs.

Claim 6

A pulse control circuit comprising: an input terminal supplied with a pulse signal; a first FET put into the conductive state in response to said pulse signal; a first time constant circuit charged when said first FET is put in the conductive state; a second FET put into the conductive state with the charging voltage of said first time constant circuit; a second time constant circuit discharging the charged electricity in said first time constant circuit when said second FET is put in the conductive state; an output terminal to deliver an output signal having a wave form in accordance with the time constants of said first and second time constant circuits, wherein said first and second FETs have polarities opposite to each other, drains, sources and gates, first and second DC power sources, the drain of said first FET is connected to said first DC power source, the drain of said second FET is connected to said second DC power source which has a polarity opposite to that of said first DC power source, and the sources of said first and second FETs connected to said first and second time constant circuits, respectively, and a constant current circuit connected to the gates of said first and second FETs.

Claim 7

A pulse control circuit according to claim 4, wherein said first time constant circuit comprises a first resistor and a capacitor, and said second time constant circuit comprises a second resistor and said capacitor.

Claim 8

A pulse control circuit according to claim 5, wherein at least one of said first and second resistors of said time constant circuits is a variable resistor.

Claim 9

A pulse control circuit according to claim 5, wherein said capacitor is a variable capacitor.

Claim 10

A pulse control circuit comprising: an input terminal supplied with a pulse signal; a first FET put into the conductive state in response to said pulse signal; a first time constant circuit charged when said first FET is put in the conductive state; a second FET put into the conductive state with the charging voltage of said first time constant circuit; a second time constant circuit discharging the charged electricity in said first time constant circuit when said second FET is put in the conductive state; an output terminal to deliver an output signal havng a wave form in accordance with the time constants of said first and second time constant circuits, wherein said first and second FETs have drains, sources and gates, said sources being connected to said first and second time constant circuits respectively, and said gates being connected to a biasing circuit including a constant current circuit connected between said first and second DC power sources and a resistor connected in series with said constant current circuit, wherein said first FET is a vertical junction structure formed of an intrinsic semiconductor region having low impurity concentration and high resistance, a first type semiconductor region having a predetermined configuration and formed on the upper portion of said intrinsic semiconductor region, and a second type semi-conductor region having high impurity concentration formed over both said first type semiconductor region and said intrinsic semiconductor region, said second FET being a vertical junction structure formed of an intrinsic semiconductor region having low impurity concentration and high resistance, a second type semiconductor region having a predetermined configuration and formed on the upper portion of the said intrinsic semiconductor region, and a first type semiconductor region having high impurity concentration formed over both said second type semiconductor region and said intrinsic semiconductor region.

Claim 11

A pulse control circuit comprising: an input terminal supplied with a pulse signal; a first FET put into the conductive state in response to said pulse signal; a first time constant circuit charged when said first FET is put in the conductive state; a second FET put into the conductive state with the charging voltage of said first time constant circuit; a second time constant circuit discharging the charged electricity in said first time constant circuit when said second FET is put in the conductive state; an output terminal to deliver an output signal havng a wave form in accordance with the time constants of said first and second time constant circuits, wherein said first and second FETs have drains, sources and gates, said sources being connected to said first and second time constant circuits respectively, and said gates being connected to a biasing circuit including a constant current circuit connected between said first and second DC power sources and a resistor connected in series with said constant current circuit, wherein said first FET is a vertical junction structure formed of an intrinsic semiconductor region having low impurity concentration and high resistance, a first type semiconductor region having a predetermined configuration and formed on the upper portion of said intrinsic semiconductor region, and a second type semi-conductor region having high impurity concentration formed over both said first type semiconductor region and said intrinsic semiconductor region, said second FET being a vertical junction structure formed of an intrinsic semiconductor region having low impurity concentration and high resistance, a second type semiconductor region having a predetermined configuration and formed on the upper portion of the said intrinsic semiconductor region, and a first type semiconductor region having high impurity concentration formed over both said second type semiconductor region and said intrinsic semiconductor region.

Claim 12

A pulse control circuit comprising: a first FET of a first polarity, a second FET of a second polarity, a first voltage source of a first polarity, a second voltage source of a second polarity, said first and second FETs being connected in series between said first and second voltage sources; a biasing circuit for applying biasing voltages to the gates of said first and second FETs, a pulse signal source supplying a pulse signal to said FETs, a first time constant circuit connected to said first FET and consisting of a first resistor and a capacitor; and a second time constant circuit connected to said second FET and consisting of a second resistor and said capacitor; said capacitor being charged through said first resistor when said first FET is in the conductive state in response to said pulse signal, and charged voltage in said capacitor being discharged through said second resistor when said second FET is in the conductive state in response to said charged voltage, said biasing circuit including first and second DC voltage sources, a constant current circuit connected between said voltage sources, and a third resistor connected in series with said constant current circuit.

Claim 13

A pulse control circuit comprising: a first FET of a first polarity, a second FET of a second polarity, a first voltage source of a first polarity, a second voltage source of a second polarity, said first and second FETs being connected in series between said first and second voltage sources; a biasing circuit for applying biasing voltages to the gates of said first and second FETs, a pulse signal source supplying a pulse signal to said FETs, a first time constant circuit connected to said first FET and consisting of a first resistor and a capacitor; and a second time constant circuit connected to said second FET and consisting of a second resistor and said capacitor; said capacitor being charged through said first resistor when said first FET is in the conductive state in response to said pulse signal, and charged voltage in said capacitor being discharged through said second resistor when said second FET is in the conductive state in response to said charged voltage, said biasing circuit including first and second DC voltage sources, a constant current circuit connected between said voltage sources, and a third resistor connected in series with said constant current circuit.

Claim 14

A pulse control circuit according to claim 9, wherein at least one of said first and second resistors is a variable resistor.

Claim 15

A pulse control circuit accordng to claim 9, wherein said capacitor is a variable capacitor.

Claim 16

A pulse control circuit according to claim 9, wherein each of said first and second FETs is a vertical junction structure having triode-type dynamic characteristics.