Layout for stable high speed semiconductor memory device

Claim 1

A high speed and high stability layout for semiconductor memory device comprising at least following circuit block elements on a semiconductor substrate: at least two substantially rectangular memory cell arrays each having first sides and second sides orthogonally crossing each other, disposed on said semiconductor substrate such that said first sides of said at least two substantially rectangular memory cell arrays are faced mutually with a space therebetween, and having a plurality of memory cells arrayed in a matrix; at least two shift register means for writing data into said memory cells and reading out data from said memory cells, said at least two shift register means being individually disposed adjacent to said faced first sides of said at least two substantially rectangular memory cell arrays; control signal lines disposed between said at least two shift register means extending along said first sides of said at least two substantially rectangular memory cell arrays; a peripheral circuit means disposed along said second sides of said at least two substantially rectangular memory cell arrays for supplying said control signal lines with control signals; and an input and output circuit means for transferring data between said at least two shift register means and circuitry which is external to said semiconductor substrate; wherein said peripheral circuit means comprises: a write control signal generator, a read control signal generator, and a shift register control signal generator; and said control signal lines comprise: a write control signal line for supplying said at least two shift register means with write control signals from said write control signal generator so as to write the data stored in said at least two shift register means into said memory cells; a read control signal line for supplying said at least two shift register means with read control signals from said write control signal generator so as to read out the data stored in said memory cells into said at least two shift register means, nd a shift register control signal line for supplying said at least two shift register means with shift register control signals from said shift register control signal generator so as to transfer the data stored in each stage of said at least two shift register means sequentially.