Rounding unit for use in arithmetic processing of floating point data

Claim 2

A rounding unit for arithmetic processing of floating point data comprisng a mantissa part and an exponent part, said unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data a mantissa part register, connected to said first data bus and to said mantissa part data bus, for storing the mantissa part of the floating point data; an exponent part register, separate from said mantissa part register and connected to said first data bus and to said exponent part data bus, for storing the exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide incremented mantissa data and outputting a carry signal when it is overflowed; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide incremented exponent data, wherein said exponent part incrementer increments the exponent part of the floating point data concurrently with incrementing of the mantissa part of the floating point data by said mantissa part incrementer; and a selection circuit connected to said mantissa part register, said exponent part register, said judging circuit, said mantissa part incrementer, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, said selection circuit orders the mantissa part register to output previously-stored constant data of which the most significant bit is "1" and the other bits are "0", when the rounding operation is raising and the carry signal is present.

Claim 3

A rounding unit as claimed in claim 1, wherein the exponent part register includes a first exponent part register for storing the exponent part of the floating point data before the rounding operation is conducted, and a second exponent part register for storing the exponent part of the floating point data after the rounding operation is completed.

Claim 4

A rounding unit as claimed in claim 2, wherein, when the carry signal is absent, the selection circuit orders the first exponent part register to output the data to the exponent part data bus and orders the second exponent part register to read the data present in the exponent part data bus, and when the carry signal is present, the selection circuit orders the exponent part incrementer to output the incremented exponent data to the exponent part data bus and orders the second exponent part register to read the data present in the exponent part data bus.

Claim 5

A rounding unit for arithmetic processing of floating point data comprising a mantissa part and an exponent part, said unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for storing the mantissa part of the floating point data, wherein the mantissa part register includes a first mantissa part register for storing the mantissa part of the floating point data before the rougind operation is conducted, a second mantissa part register for storing the mantissa part of the floating point data after the rounding operation is completed, and a constant register for storing the constant data; an exponent part register, connected to said first data bus and to said exponent part data bus, for storing the exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide incremented mantissa data and outputting a carry signal when it is overflowed; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide incremented exponent data; and a selection circuit connected to said mantissa part register, said exponent part register, said judging circuit, said mantissa part incrementer, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, said selection circuit orders the mantissa part register to output previously-stored constant data of which the most significant bit is "1" and the other bits are "0", when the rounding operation is raising and the carry signal is present.

Claim 6

A rounding unit for arithmetic processing of floating point data comprising a mantissa part and an exponent part, said unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for storing the mantissa part of the floating point data, wherein the mantissa part register includes a first mantissa part register for storing the mantissa part of the floating point data before the rougind operation is conducted, a second mantissa part register for storing the mantissa part of the floating point data after the rounding operation is completed, and a constant register for storing the constant data; an exponent part register, connected to said first data bus and to said exponent part data bus, for storing the exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide incremented mantissa data and outputting a carry signal when it is overflowed; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide incremented exponent data; and a selection circuit connected to said mantissa part register, said exponent part register, said judging circuit, said mantissa part incrementer, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, said selection circuit orders the mantissa part register to output previously-stored constant data of which the most significant bit is "1" and the other bits are "0", when the rounding operation is raising and the carry signal is present.

Claim 7

A rounding unit as claimed in claim 4, wherein, when the rounding operation is truncating, the selection circuit orders the first mantissa part register to output the data stored therein to the mantissa part data bus and the second mantissa part register to read the data present in the mantissa part bus; when the rounding operation is raising, but the carry signal is absent, the selection circuit orders the mantissa part incrementer to output the incremented mantissa data to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part data bus; and when the rounding operation is raising and the carry signal is present, the selection circuit orders the constant register to output the constant data to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa data bus.

Claim 8

A rounding unit for arithmetic processing of floating point data comprising a mantissa part and an exponent part, said unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for storing the mantissa part of the floating point data; an exponent part register, connected to said first data bus and to said exponent part data bus, for storing the exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide incremented mantissa data and outputting a carry signal when it is overflowed; adjusting means, connected to the mantissa part incrementer, for receiving the carry signal and the the incremented mantissa data, and for modifying the modified mantissa data by adding "1" to the most significant bit of the incremented mantissa data when the carry signal is present, wherein said selection circuit orders the mantissa part register to read the modified data, when the rounding operation is raising and the carry signal is present; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating pint data to provide incremented exponent data; and a selection circuit connected to said mantissa part register, said exponent part register, said judging circuit, said mantissa part incrementer, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, said selection circuit orders the mantissa part register to output previously-stored constant data of which the most significant bit is "1" and the other bits are "0", when the rounding operation is raising and the carry signal is present.

Claim 9

A rounding unit for arithmetic processing of floating point data comprising a mantissa part and an exponent part, said unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for storing the mantissa part of the floating point data; an exponent part register, connected to said first data bus and to said exponent part data bus, for storing the exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide incremented mantissa data and outputting a carry signal when it is overflowed; adjusting means, connected to the mantissa part incrementer, for receiving the carry signal and the the incremented mantissa data, and for modifying the modified mantissa data by adding "1" to the most significant bit of the incremented mantissa data when the carry signal is present, wherein said selection circuit orders the mantissa part register to read the modified data, when the rounding operation is raising and the carry signal is present; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating pint data to provide incremented exponent data; and a selection circuit connected to said mantissa part register, said exponent part register, said judging circuit, said mantissa part incrementer, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, said selection circuit orders the mantissa part register to output previously-stored constant data of which the most significant bit is "1" and the other bits are "0", when the rounding operation is raising and the carry signal is present.

Claim 10

A rounding unit as claimed in claim 6, wherein the mantissa part register includes a first mantissa part register for storing the mantissa part of the floating point data before the rounding operation is conducted, and a second mantissa part register for storing the mantissa part of the floating point data after the rounding operation is completed.

Claim 11

A rounding unit as claimed in claim 6, wherein, when the rounding opeation is truncating, the selection circuit orders the first mantissa part register to output the data stored therein to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part data bus; when the rounding operation is raising, but the carry signal is absent, the selection circuit orders the mantissa part incrementer to output the incremented mantissa data to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part data bus; and when the rounding operation is raising and the carry signal is present, the selection circuit orders the adjusting means to output the adjusted incremented mantissa data to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part data bus.

Claim 12

A rounding unit as claimed in claim 7, wherein, when the rounding operation is raising, but the carry signal is absent, the incremented mantissa data is outputted as it is through the adjusting means to the mantissa part data bus.

Claim 13

A rounding unit for an arithmetic unit for processing floating point data comprising a mantissa part and an exponent part, said rounding unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data, said arithmetic unit being connected to all of said first data bus, said mantissa part data bus, and said exponent part data bus; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for receiving from the arithmetic unit the mantissa part of the floating point data and outputting thereto the rounded mantissa part of the floating point data; a constant register, connected to said mantissa part data bus, for storing constant data of which the most significant bit is "1" and the other bits are "0", an exponent part register, connected to said first data bus and to said exponent part data bus, for receiving from the arithmetic unit the exponent part of the floating point data and outputting thereto the rounded exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide incremented mantissa data and outputting a carry signal when it is overflowed; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide incremented exponent data; and a selection circuit connected to said mantissa part register, said exponent part register, said constant register, said judging circuit, said mantissa part incrementer, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, said selection circuit orders transfer of the constant data from the constant register to the mantissa part register, when the rounding operation is raising and the carry signal is present.

Claim 14

A rounding unit for an arithmetic unit for processing floating point data comprising a mantissa part and an exponent part, said rounding unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data, said arithmetic unit being connected to all of said first data bus, said mantissa part data bus, and said exponent part data bus; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for receiving from the arithmetic unit the mantissa part of the floating point data and outputting thereto the rounded mantissa part of the floating point data; a constant register, connected to said mantissa part data bus, for storing constant data of which the most significant bit is "1" and the other bits are "0", an exponent part register, connected to said first data bus and to said exponent part data bus, for receiving from the arithmetic unit the exponent part of the floating point data and outputting thereto the rounded exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for receiving and incrementing the mantissa part of the floating point data to provide incremented mantissa data and outputting a carry signal when it is overflowed; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide incremented exponent data; and a selection circuit connected to said mantissa part register, said exponent part register, said constant register, said judging circuit, said mantissa part incrementer, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, said selection circuit orders transfer of the constant data from the constant register to the mantissa part register, when the rounding operation is raising and the carry signal is present.

Claim 15

A rounding unit as claimed in claim 10, said mantissa part register including a first mantissa part register for receiving from the arithmetic unit and storing therein the mantissa part of the floating point data before the rounding operation is conducted and a second mantissa part register for storing and outputting to the arithmetic unit the rounded mantissa part of the floating point data.

Claim 16

A rounding unit as claimed in claim 11, wherein, when the rounding operation is truncating, the selection circuit orders the first mantissa part register to output the data stored therein to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part data bus; when the rounding operation is raising, but the carry signal is absent, the selection circuit orders the mantissa part incrementer to output the incremented mantissa data to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part data bus; and when the rounding operation is raising and the carry signal is present, the selection circuit orders the constant register to output the constant data to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa data bus.

Claim 17

A rounding unit as claimed in claim 10, wherein the exponent part register includes a first exponent part register for receiving from the arithmetic unit and storing the exponent part of the floating point data before the rounding operation is conducted, and a second exponent part register for storing and outputting to the arithmetic unit the rounded exponent part of the floating point data after the rounding operation is completed.

Claim 18

A rounding unit as claimed in claim 13, wherein, when the carry signal is absent, the selection circuit orders the first exponent part register to output the data to the exponent part data bus and orders the second exponent part register to read the data present in the exponent part data bus; and when the carry signal is present, the selection circuit orders the exponent part incrementer to output the incremented exponent data to the exponent part data bus and orders the second exponent part register to read the data present in the exponent part data bus.

Claim 19

A rounding unit for an arithmetic unit for processing floating point data comprising mantissa part data and exponent part data, said rounding unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data, said arithmetic unit being connected to all of said first data bus, said mantissa part data bus, and said exponent part data bus; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for receiving from the arithmetic unit the mantissa part of the floating point data and outputting thereto the rounded mantissa part of the floating point data; an exponent part register, connected to said first data bus and to said exponent part data bus, for receiving from the arithmetic unit the exponent part of the floating point data and outputting thereto the rounded exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for incrementing the mantissa part of the floating point data and outputting a carry signal when it is overflowed; an adjusting means connected to the mantissa part incrementer and to said mantissa part data bus, to receive the carry signal and the incremented mantissa data, and for modifying the incremented mantissa data by adding "1" to the most significant bit of the incremented mantissa data when the carry signal is present; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide incremented exponent data; and a selection circuit, connected to said mantissa part register, said exponent part register, said judging circuit, said mantissa part incrementer, said adjusting means, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, orders the mantissa part register to read the data modified by the adjusting means, when the rounding operation is raising and the carry signal is present.

Claim 20

A rounding unit for an arithmetic unit for processing floating point data comprising mantissa part data and exponent part data, said rounding unit comprising: a first data bus for transmitting data; a mantissa part data bus for transmitting the mantissa part of the floating point data; an exponent part data bus for transmitting the exponent part of the floating point data, said arithmetic unit being connected to all of said first data bus, said mantissa part data bus, and said exponent part data bus; a mantissa part register, connected to said first data bus and to said mantissa part data bus, for receiving from the arithmetic unit the mantissa part of the floating point data and outputting thereto the rounded mantissa part of the floating point data; an exponent part register, connected to said first data bus and to said exponent part data bus, for receiving from the arithmetic unit the exponent part of the floating point data and outputting thereto the rounded exponent part of the floating point data; a judging circuit, connected to said first data bus, for judging whether the rounding operation is raising or truncating; a mantissa part incrementer, connected to said mantissa part data bus, for incrementing the mantissa part of the floating point data and outputting a carry signal when it is overflowed; an adjusting means connected to the mantissa part incrementer and to said mantissa part data bus, to receive the carry signal and the incremented mantissa data, and for modifying the incremented mantissa data by adding "1" to the most significant bit of the incremented mantissa data when the carry signal is present; an exponent part incrementer, connected to said exponent part data bus, for receiving and incrementing the exponent part of the floating point data to provide incremented exponent data; and a selection circuit, connected to said mantissa part register, said exponent part register, said judging circuit, said mantissa part incrementer, said adjusting means, and said exponent part incrementer, wherein, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, orders the mantissa part register to read the data modified by the adjusting means, when the rounding operation is raising and the carry signal is present.

Claim 21

A rounding unit as claimed in claim 15, said mantissa part register including a first mantissa part register for receiving from the arithmetic unit and storing therein the mantissa part of the floating point data before the rounding operation is conducted, and a second mantissa part register for storing therein and outputting to the arithmetic unit the rounded mantissa part of the floating point data.

Claim 22

A rounding unit as claimed in claim 16, wherein, when the rounding operaiton is truncating, the selection circuit orders the first mantissa part register to output the data stored therein to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part bus; when the rounding operation is raising, the selection circuit orders the adjusting means to output the adjusted data to the mantissa part data bus and orders the second mantissa part register to read the data present in the mantissa part data bus.

Claim 23

A rounding unit as claimed in claim 16, wherein, when the rounding operation is raising, but the carry signal is absent, the incremented mantissa data is outputted as it is through the adjusting means to the mantissa part data bus.

Claim 24

A rounding unit as claimed in claim 15, wherein the exponent part register includes a first exponent part register for receiving from the arithmetic unit and storing therein the exponent part of the floating point data before the rounding operation is conducted, and a second exponent part register for storing therein and outputting to the arithmetic unit the exponent part of the floating point data after the rounding operation is completed.

Claim 25

A rounding unit as claimed in claim 19, wherein, when the carry signal is absent, the selection circuit orders the first exponent part register to output the data to the exponent part data bus and orders the second exponent part register to read the data present in the exponent part data bus; and when the carry signal is present, the selection circuit orders the exponent part incrementer to output the incremented exponent data to the exponent part data bus and orders the second exponent part register to read the data present in the exponent part data bus.