Semiconductor device having ultrahigh-mobility

Claim 2

A semiconductor device comprising: a semiconductor substrate; first and second respective semiconductor layers formed on said semiconductor substrate, said first and second semiconductor layers forming therebetween aheterojunction and wherein a carrier transfer region is formed adjacent to said heterojunction; first and second means for transmitting and receiving carriers and being formed on opposite ends of said carrier transfer region and in contact therewith; a third semiconductor layer including a plurality of stripe regions formed on said second semiconductor layer, each of said stripe regions being formed on a portion of said second semiconductor layer with its length in a direction connecting said first and second means and wherein said plurality of stripe regions are parallelly spaced-apart and periodically disposed on said second semiconductor layer in a direction perpendicular to a direction connecting said first and second means; and carrier controlling means for controlling the carriers in said carried transfer region, said carrier controlling means being formed on said plurality of stripe regions and on said second semiconductor layer region between respective pairs of stripe regions on a portion of said semiconductor device between said first and second means.

Claim 3

A semiconductor device according to claim 1, wherein said plurality of stripe regions are periodically disposed with a period having a range of 5 to 500 nm.

Claim 4

A semiconductor device according to claim 2, wherein said period is approximately 50 nm and the width of each stripe region is about 25 nm.

Claim 5

A semiconductor device according to claim 2, wherein said carrier controlling means comprises a gate electrode overlying a central portion of said semiconductor device and said first and second means comprise a source and drain region and wherein said semiconductor device is a field-effect transistor of ultrahigh-mobility.

Claim 6

A semiconductor device according to claim 4, wherein said semiconductor substrate is comprised of semi-insulating GaAs material, said first layer is of non-doped type GaAs material, said second layer is comprised of n-type Al 0 .3 Ga 0 .7 As material and said third semiconductor layer is comprised of n-type GaAs material which contains Si.

Claim 7

A semiconductor device according to claim 5, wherein said Si has a doping concentration of about 2×10 18 cm -3 and wherein each of said plurality of stripe regions having a thickness of about 30 nm, a width of about 25 nm and are periodically on said second semiconductor layer about every 50 nm.

Claim 8

A semiconductor device according to claim 5, wherein respective channels between the source and drain are formed in those portions of said semiconductor device having said stripe regions and in those portions having no stripe layers a barrier region is formed, and wherein said carrier transfer region comprises a two-dimensional-electron-gas layer having a density of carriers, induced near the interface of said GaAs layer and said Al 0 .3 Ga 0 .7 As layer, which is modulated in accordance with the period of said plurality of stripe regions thereby resulting in substantial electron flow movement only in the direction of a respective channel.

Claim 9

A semiconductor device comprising: a semiconductor substrate; first and second respective semiconductor layers formed on said semiconductor substrate, said first and second semiconductor layers forming therebetween a heterojunction and wherein a carrier transfer region is formed adjacent to said heterojunction; first and second means for transmitting and receiving carriers and being formed on opposite ends of said carrier transfer region and in contact therewith; a third semiconductor layer including a plurality of stripe regions formed on said second semiconductor layer, each region being formed on a portion of said second semiconductor layer with its length in a direction connecting said first and second means and wherein said plurality of stripe regions are parallelly and periodically disposed on said second semiconductor layer in a direction perpendicular to a direction connecting said first and second means forming a pattern of stripe regions having a periodic structure and of a material and doping concentration such that there results a substantial charge flow movement only in the direction along the length of the respective stripe regions and on the portions wherein the stripe regions are formed; and carrier controlling means for controlling the carriers in said carrier transfer region, said carrier controlling means being formed on said third semiconductor layer on a portion thereof between said first and second means.

Claim 10

A semiconductor device comprising: a semiconductor substrate; first and second respective semiconductor layers formed on said semiconductor substrate, said first and second semiconductor layers forming therebetween a heterojunction and wherein a carrier transfer region is formed adjacent to said heterojunction; first and second means for transmitting and receiving carriers and being formed on opposite ends of said carrier transfer region and in contact therewith; a third semiconductor layer including a plurality of stripe regions formed on said second semiconductor layer, each region being formed on a portion of said second semiconductor layer with its length in a direction connecting said first and second means and wherein said plurality of stripe regions are parallelly and periodically disposed on said second semiconductor layer in a direction perpendicular to a direction connecting said first and second means forming a pattern of stripe regions having a periodic structure and of a material and doping concentration such that there results a substantial charge flow movement only in the direction along the length of the respective stripe regions and on the portions wherein the stripe regions are formed; and carrier controlling means for controlling the carriers in said carrier transfer region, said carrier controlling means being formed on said third semiconductor layer on a portion thereof between said first and second means.

Claim 11

A semiconductor device according to claim 8, wherein said plurality of stripe regions are parallelly spaced-apart and periodically disposed on said second semiconductor layer in a direction perpendicular to a direction connecting said first and second means; and said carrier controlling means being formed on both said plurality of stripe regions and on said second semiconductor layer between respective pairs of stripe regions on a portion of said semiconductor device between said first and second means.

Claim 12

A semiconductor device according to claim 9, wherein said carrier controlling means comprises a gate electrode overlying a central portion of said semiconductor device and said first and second means comprise a source and drain region and wherein said semiconductor device is a field-effect transistor of ultrahigh-mobility.

Claim 13

A semiconductor device according to claim 8, wherein said plurality of stripe regions are periodically disposed with a period having a range of 5 to 500 nm.

Claim 14

A semiconductor device according to claim 8, wherein said plurality of stripe regions are comprised of a first group of stripe regions of a first type of layer and a second group of stripe regions having a different doping characteristic than said first group is formed in said first type of layer, said first and second groups being a parallelly disposed alternating planar arrangement wherein a stripe region of one group is disposed between and contiguous with a pair of stripe regions of the other group.

Claim 15

A semiconductor device according to claim 12, wherein said carrier controlling means comprises a gate electrode overlying a central portion of said semiconductor device and said first and second means comprise a source and drain region and wherein said semiconductor device is a field-effect transistor of ultrahigh-mobility.

Claim 16

A semiconductor device according to claim 13, wherein said first type of layer is comprised of a GaAs layer and said second group is comprised of Zn-doped regions periodically formed in said GaAs layer such that there results in a periodic arrangement of alternating stripe regions.

Claim 17

A semiconductor device according to claim 14, wherein said Zn-doped regions are formed by ion implantation.

Claim 18

A semiconductor device according to claim 14, wherein said period is approximately 50 nm and the width of each stripe region is about 25 nm.

Claim 19

A semiconductor device comprising: a semiconductor substrate; first and second respective semiconductor layers formed on said semiconductor substrate, said first and second semiconductor layers forming therebetween a heterojunction and wherein a carrier transfer region is formed adjacent to said heterojunction; first and second means for transmitting and receiving carriers and being formed on opposite ends of said carrier transfer region and in contact therewith; a third semiconductor layer formed on said second semiconductor layer including a plurality of stripe regions forming a periodic planar pattern structure comprised of a first group of stripe regions of a first type of layer and a second group of stripe regions having a different doping characteristic than said first group formed on said first type of layer, said first and second groups of stripe regions being a parallelly disposed alternating arrangement of strip regions of said second group periodically formed on said first type of layer thereby effecting a periodic planar pattern structure of a stripe region of one group disposed between a pair of stripe regions of the other group, and wherein each of said plurality of regions is formed such that its length is in a direction connecting said first and second means thereby effecting in a channel therethrough and said parallelly disposed alternating arrangement is in a direction perpendicular to a direction connecting said first and second means; and carrier controlling means for controlling the carriers in said carrier transfer region, said carrier controlling means being formed on said third semiconductor layer on a portion thereof between said first and second means.

Claim 20

A semiconductor device comprising: a semiconductor substrate; first and second respective semiconductor layers formed on said semiconductor substrate, said first and second semiconductor layers forming therebetween a heterojunction and wherein a carrier transfer region is formed adjacent to said heterojunction; first and second means for transmitting and receiving carriers and being formed on opposite ends of said carrier transfer region and in contact therewith; a third semiconductor layer formed on said second semiconductor layer including a plurality of stripe regions forming a periodic planar pattern structure comprised of a first group of stripe regions of a first type of layer and a second group of stripe regions having a different doping characteristic than said first group formed on said first type of layer, said first and second groups of stripe regions being a parallelly disposed alternating arrangement of strip regions of said second group periodically formed on said first type of layer thereby effecting a periodic planar pattern structure of a stripe region of one group disposed between a pair of stripe regions of the other group, and wherein each of said plurality of regions is formed such that its length is in a direction connecting said first and second means thereby effecting in a channel therethrough and said parallelly disposed alternating arrangement is in a direction perpendicular to a direction connecting said first and second means; and carrier controlling means for controlling the carriers in said carrier transfer region, said carrier controlling means being formed on said third semiconductor layer on a portion thereof between said first and second means.

Claim 21

A semiconductor device according to claim 17, wherein said plurality of stripe regions are periodically disposed with a period having a range of 5 to 500 nm.

Claim 22

A semiconductor device according to claim 18, wherein said carrier controlling means comprises a gate electrode overlying a central portion of said semiconductor device and said first and second means comprise a source and drain region and wherein said semiconductor device is a field-effect transistor of ultrahigh-mobility.

Claim 23

A semiconductor device according to claim 19, wherein said first type of layer is comprised of a GaAs layer and said second group is comprised of Zn-doped regions periodically formed in said GaAs layer such that there results in a periodic arrangement of alternating stripe regions.

Claim 24

A semiconductor device according to claim 20, wherein said Zn-doped regions are formed by ion implantation.

Claim 25

A semiconductor device according to claim 26, wherein said semiconductor substrate is comprised of semi-insulating GaAs material, said first layer is of non-doped type GaAs material, said second layer is comprised of n-type Al 0 .3 Ga 0 .7 As material and said third semiconductor layer is comprised of n-type GaAs material which contains Zn periodically disposed for forming said first and second groups of stripe regions.

Claim 26

A semiconductor device according to claim 19, wherein said semiconductor substrate is comprised of semi-insulating GaAs material, said first layer is of non-doped type GaAs material, said second layer is comprised of Be-doped p-type Al 0 .3 Ga 0 .7 As material and said third semiconductor layer is comprised of p-type GaAs material which contains Si periodically disposed for forming said first and second groups of stripe regions.

Claim 27

A semiconductor device according to claim 23, wherein said period is approximately 50 nm and the width of each stripe region is about 25 nm.

Claim 28

A semiconductor device according to claim 22, wherein said period is approximately 50 nm and the width of each stripe region is about 25 nm.

Claim 29

A semiconductor device comprising: a semiconductor region; an insulating layer formed on said semiconductor region, and a carrier transfer region is formed adjacent to an interface between said semiconductor region and said insulating layer; first and second means for transmitting and receiving carriers and being formed on opposite ends of said carrier transfer region and in contact therewith; said insulating layer being comprised of a plurality of stripe regions formed on said insulating layer each being spaced apart and having a thickness greater than the thickness of the insulating layer between each pair of said stripe regions and wherein each stripe region is formed so that its length is disposed in a direction connecting said first and second means and said plurality of stripe regions are parallelly spaced-apart and periodically disposed in a direction perpendicular to a direction connecting said first and second means; and carrier controlling means for controlling the carriers in said carrier transfer region, said carrier controlling means being formed on said plurality of stripe regions and on the insulating layer between pairs of stripe regions on a portion of said semiconductor device between said first and second means.

Claim 30

A semiconductor device comprising: a semiconductor region; an insulating layer formed on said semiconductor region, and a carrier transfer region is formed adjacent to an interface between said semiconductor region and said insulating layer; first and second means for transmitting and receiving carriers and being formed on opposite ends of said carrier transfer region and in contact therewith; said insulating layer being comprised of a plurality of stripe regions formed on said insulating layer each being spaced apart and having a thickness greater than the thickness of the insulating layer between each pair of said stripe regions and wherein each stripe region is formed so that its length is disposed in a direction connecting said first and second means and said plurality of stripe regions are parallelly spaced-apart and periodically disposed in a direction perpendicular to a direction connecting said first and second means; and carrier controlling means for controlling the carriers in said carrier transfer region, said carrier controlling means being formed on said plurality of stripe regions and on the insulating layer between pairs of stripe regions on a portion of said semiconductor device between said first and second means.

Claim 31

A semiconductor device according to claim 26, wherein said plurality of stripe regions are periodically disposed with a period having a range of 5 to 500 nm.

Claim 32

A semiconductor device according to claim 26, wherein said carrier controlling means comprises a gate electrode overlying a central portion of said insulating layer and said first and second means comprise a source and drain region and wherein said semiconductor device is a MOSFET of ultrahigh-mobility.

Claim 33

A semiconductor device according to claim 28, wherein said MOSFET is of the n-channel type, the resulting channel formed being in a direction parallel to the length of the respective stripe regions and whereby greater directional mobility control results.

Claim 34

A semiconductor device according to claim 28, wherein said MOSFET is of the p-channel type, the resulting channel formed being in a direction parallel to the length of the respective stripe regions and whereby greater directional mobility control results.

Claim 35

A semiconductor device according to claim 28, wherein said insulating layer is comprised of an insulator film in the form of substantially rectangular notches in which the thick portions corresponding to said stripe regions are about 30 nm thick and the thin portions are about 15 nm thick, and wherein the period of the parallel arrangement of said plurality of stripe regions is about 20 nm.