EP0212295A2
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Monocrystalline semiconductor superlattice structures
Assignee: International Business Machines Corp
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Filing: 1986-07-22
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Granted: —
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Expires: 2006-07-22
Abstract
Abstract A semiconductor superlattice (1) is provided with a one-dimensional carrier path (a) at the intersection of low energy level layers (5, 7) of the superlattice. A group of layers in a first crystallographic direction (Y) comprises a low energy level layer (5) bounded by two higher energy level layers (4, 6). A series of layers in a second crystallographic direction (2) different from the first comprises a lower energy level layer (7) immediately adjacent the layers of the group of layers (4, 5, 6). The lower energy layer is bounded by a higher energy level layer (8). The low and higher energy level layers can be formed of Ga 1-x Al x A s where x is larger for higher energy level layers. The lower energy level layer can be formed from GaAs of 10nm thickness. Conductivity modulation through an adjacent exposed surface (11) can then be employed for controlling electron and hole movement in the path to define a quantum pipeline carrier path. Control and contacting electrodes may be positioned on the exposed surfaces.
Inventors
- 👤 Leroy Li-Gong Chang
- 👤 Leo Esaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 04:19
CPC Classifications
B; B82; B82Y; B82Y10/00; H; H10; H10D; H10D30/00; H10D30/40; H10D30/43; H10D62/00; H10D62/80; H10D62/81; H10D62/812; H10D62/813; H10D62/815; H10D62/8161
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
162 words
A monocrystalline semiconductor superlattice structure comprising in combination: a first series of layers (4, 5, 6) in a first crystallographic direction comprising at least one group of layers having a first layer (4) with a first energy level (E c 'x₁)) which is bounded by second and third layers (4, 6) having energy levels (E c (x₂)) higher than the first energy level; and at least one additional series of layers (7, 8), each in a crystallographic direction different from the first direction, at least one additional series of layers having a fourth layer (7) immediately adjacent the edges of the layers of the first series of layers, the fourth layer having an energy level (E c ) lower than the first energy level and being bounded by a fifth layer (8) having an energy level (E c (x₃)) higher than the first energy level whereby a one-dimensional carrier path (9) is defined at the intersection of the first and fourth layers.
Claim 2
Dependent Claim
162 words
A monocrystalline semiconductor superlattice structure comprising in combination: a first series of layers (4, 5, 6) in a first crystallographic direction comprising at least one group of layers having a first layer (4) with a first energy level (E c 'x₁)) which is bounded by second and third layers (4, 6) having energy levels (E c (x₂)) higher than the first energy level; and at least one additional series of layers (7, 8), each in a crystallographic direction different from the first direction, at least one additional series of layers having a fourth layer (7) immediately adjacent the edges of the layers of the first series of layers, the fourth layer having an energy level (E c ) lower than the first energy level and being bounded by a fifth layer (8) having an energy level (E c (x₃)) higher than the first energy level whereby a one-dimensional carrier path (9) is defined at the intersection of the first and fourth layers.
Claim 3
Dependent Claim
28 words
A structure according to claim 1 comprising, in addition, an exposed control surface (11) for each additional series of layers in current influencing proximity to the fourth layer.
Claim 4
Dependent Claim
27 words
A structure according to claim 2 wherein said current influencing proximity is established by the thickness of the fifth and possible subsequent layers in each additional series.
Claim 5
Dependent Claim
30 words
A structure according to any one of the preceding claims wherein layers having the first and the lower energy levels are narrower than the layers having the higher energy levels.
Claim 6
Dependent Claim
59 words
A structure according to any one of the preceding claims wherein the second, first and third layers are, respectively, of Ga 1-x2 Al x2 As, GA 1-x1 Al x1 As and Ga 1-x2 As and Ga1-x₂As where x₂>x₁ and wherein the fourth layer is GaAs and the fifth layer is Ga 1-x3 Al x3 As where x3 ≧ x2.
Claim 7
Dependent Claim
24 words
A structure according to any one of the preceding claims wherein the width of said lower energy superlattice layers that intersect is 10 nm.
Claim 8
Dependent Claim
19 words
A structure according to any one of the preceding claims wherein control surface is 50 nm from said pipeline.
Claim 9
Dependent Claim
74 words
A semiconductor device comprising a structure according to any one of claims 2 to 7 wherein ohmic external electrodes means (12) are located at separated points along the control path and control means are positioned on the control surface in current influencing proximity to the path, positioned intermediate said separated points and operable to alter the carrier population in the carrier path, whereby the carrier path defines a one dimensional quantum pipeline path (9).
Claim 10
Dependent Claim
85 words
A process of forming a multidirectional superlattice structure comprising in combination the steps of: fabricating a series of different thickness epitaxial semiconductor superlattice layers in a first crystallographic direction (4, 5, 6); establishing at least one growth plane of growth quality surface texture on the crystal of said first series of layers, said plane being in a crystallographic direction different from said first crystallographic direction; and growing at least one subsequent series of superlattice layers (7, 8) with controlled thickness on each said growth plane.
Claim 11
Dependent Claim
85 words
A process of forming a multidirectional superlattice structure comprising in combination the steps of: fabricating a series of different thickness epitaxial semiconductor superlattice layers in a first crystallographic direction (4, 5, 6); establishing at least one growth plane of growth quality surface texture on the crystal of said first series of layers, said plane being in a crystallographic direction different from said first crystallographic direction; and growing at least one subsequent series of superlattice layers (7, 8) with controlled thickness on each said growth plane.
Claim 12
Dependent Claim
141 words
A process according to claim 9 wherein in the first series of layers there is formed at least one group of layers comprising a first layer (5) with a first energy level E c (x₁) and a first width (d₁) which is bounded by second and third layers (4, 6) which are thicker (d₂) than the first layer and have an energy level (E c (x₂)) higher than the first energy level and wherein, in one subsequent series of layers, a fourth layer (7) is formed immediately adjacent the growth crystal of the first series of layers, the fourth layer being narrower (d₀) than the second and third layers and having an energy level (E c ) lower than the first energy level, whereby a one dimensional carrier path (9) is defined at the intersection of the first and fourth layers.
Claim 13
Dependent Claim
56 words
A process according to claim 10 wherein the thickness of a fifth layer (8) which has a higher energy level (E c (x₃)) , subsequent to the fourth layer in the subsequent series, is controlled to a dimension enabling a control surface of the fifth layer to be in current influencing proximity to the carrier path.
Claim 14
Dependent Claim
31 words
A process according to either claim 1 or claim 11 wherein the layers of the group are defined by changes in the relative amount of one element of a three-element compound.
Claim 15
Dependent Claim
51 words
A process according to claim 12 wherein the first series is made up of layers of GaAlAs with higher concentrations of Al in higher energy level layers, and wherein the fourth layer is formed from GaAs and the fifth and possible subsequent layers in the subsequent series is formed from GaAlAs.
Claim 16
Dependent Claim
44 words
A process according to claim 13 including deposition of a control electrode (12) on the exposed surface of the subsequent series of layers and the formation of reach through connections to the carrier path whereby the carrier path defines a one-dimensional quantum pipeline path.
References Cited (Backward Citations)
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