Patent US4785205A successfully refreshed from Google Patents.
US4785205A
Expired / Lapsed
US
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High speed ECL to CMOS converter
Assignee: NCR Voyix Corp
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Filing: 1987-06-29
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Granted: 1988-11-15
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Expires: 2007-06-29
Abstract
Abstract An ECL to CMOS converter which connects the ECL input signal directly to the source electrode of a MOS gate, and the gate electrode of the MOS gate is independently regulated by connection to a reference voltage that is current sinked through a D.C. path to the negative CMOS voltage supply terminal. The drain electrode of the MOS gate is connected to the input of a CMOS inverter to provide the necessary logic level shift. Another MOS gate provides a D.C. signal path by connecting the input of the CMOS inverter to the negative CMOS voltage supply terminal.
Inventors
- 👤 Ikuo J. Sanwo
- 👤 Mukesh B. Suthar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
228 words
An ECL to CMOS converter for converting ECL logic level signals to CMOS logic level signals comprised of: a first MOS gate, of first conductivity type, having source, drain, and gate electrodes, the source electrode connected to receive ECL logic level signals; a second MOS gate, of first conductivity type, having source, drain, and gate electrodes, the drain electrode connected to the gate electrode, the source electrode connected to a biasing voltage, and the drain and gate electrodes further connected to the gate electrode of said first MOS gate; a first and a second power terminal having voltage levels thereat corresponding to high and low CMOS logic levels, respectively; a current sink connected between the drain and gate electrodes of said second MOS gate and said second power terminal; a third MOS gate, of second conductivity type, having source, drain, and gate electrodes, the drain electrode connected to the drain electrode of said first MOS gate, the source electrode connected to said second power terminal and the gate electrode connected to said first power terminal; and a complementary inverter circuit connected between said first and said second power terminals, said inverter circuit having an input connected to the drain of said first MOS gate, and an output for providing CMOS logic level signals in response to the ECL logic level signals at the source of said MOS gate.
Claim 2
Dependent Claim
228 words
An ECL to CMOS converter for converting ECL logic level signals to CMOS logic level signals comprised of: a first MOS gate, of first conductivity type, having source, drain, and gate electrodes, the source electrode connected to receive ECL logic level signals; a second MOS gate, of first conductivity type, having source, drain, and gate electrodes, the drain electrode connected to the gate electrode, the source electrode connected to a biasing voltage, and the drain and gate electrodes further connected to the gate electrode of said first MOS gate; a first and a second power terminal having voltage levels thereat corresponding to high and low CMOS logic levels, respectively; a current sink connected between the drain and gate electrodes of said second MOS gate and said second power terminal; a third MOS gate, of second conductivity type, having source, drain, and gate electrodes, the drain electrode connected to the drain electrode of said first MOS gate, the source electrode connected to said second power terminal and the gate electrode connected to said first power terminal; and a complementary inverter circuit connected between said first and said second power terminals, said inverter circuit having an input connected to the drain of said first MOS gate, and an output for providing CMOS logic level signals in response to the ECL logic level signals at the source of said MOS gate.
Claim 3
Dependent Claim
163 words
An ECL to CMOS conveter, according to claim 1, wherein said current sink is comprised of: a fourth MOS gate, of second conductivity type, having source, drain, and gate electrodes, the drain connected to the drain and gate of said second MOS gate, the source connected to said second power terminal; fifth and sixth MOS gates, of second conductivity type, having source, drain, and gate electrodes, the gate and drain electrodes of said fifth MOS gate connected to the gate electrode of said fourth MOS gate, the drain and gate of said sixth MOS gate connected to the source of said fifth MOS gate, and the source of said sixth MOS gate connected to said second power terminal; and a seventh MOS gate, of first conductivity type, having source, drain, and gate electrodes, the gate electrode connected to said second power terminal, the source electrode connected to said first power terminal and the drain connected to the gate of said fourth MOS gate.
Claim 4
Dependent Claim
33 words
An ECL to CMOS converter, according to claim 1, wherein said current sink is comprised of a resistor connected between the drain electrode of said second MOS gate and said second power terminal.
Claim 5
Dependent Claim
101 words
An ECL to CMOS converter, according to claim 1, wherein said complementary inverter circuit is comprised of: a P-channel MOS gate, having source, drain, and gate electrodes; and an N-channel MOS gate, having source, drain, and gate electrodes, the gate electrode connected to the gate electrode of said P-channel MOS gate and the drain of said first MOS gate, the drain and source of said P-channel and said N-channel MOS gates, respectively, connected together to provide an output, the source and drain of said P-channel and said N-channel MOS gates, respectively, connected to said first and said second power terminals, respectively.
Claim 6
Dependent Claim
27 words
An ECL to CMOS converter, according to claim 1, wherein the size of said first MOS gate is equal to the size of said second MOS gate.
Claim 7
Dependent Claim
37 words
An ECL to CMOS converter, according to claim 1, wherein the biasing voltage is fixed at one-half the sum of the voltage levels of the ECL low logic level signal and the ECL high logic level signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |