Buffer circuit having decreased current consumption

Claim 1

A buffer circuit for a semiconductor integrated circuit having first and second nodes (Vcc, Vss) which are supplied with first and second voltages respectively, an input node (D1) for receiving an input current from the integrated circuit, and an output node (D out ) for outputting an output current responsive to the input current, said buffer circuit comprising: load transistor means (Q20, Q21, Q80) including a plurality of load transistors coupled in parallel between said output node and said first node, and having first and second states, for increasing the input current of the buffer circuit when said load transistor means is in one of said first and second states; drive transistors means (Q27, Q28, Q82) including a plurality of drive transistors coupled in parallel between said output node and said second node, and having first and second corresponding states, for increasing the input current of the buffer circuit when said load transistor means is in the same state as said load transistor means; and first switching means (17, 20) for sequentially switching said plurality of load transistors from the first state to the second state at predetermined delay times and from the second state to the first state simultaneously; second switching means (21, 24) for sequentially switching said plurality of drive transistors from the first state to the second state at predetermined delay times and from the second state to the first state simultaneously.