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US4782247A
Expired / Lapsed
US
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Decoder circuit having a variable power supply
Assignee: Fujitsu Ltd
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Filing: 1985-07-29
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Granted: 1988-11-01
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Expires: 2005-07-29
Abstract
Abstract A decoder circuit fabricated in an IC memory chip and provided to respective word-lines and respective bit-lines of an IC memory matrix fabricated in the IC memory chip, is provided for selecting an EPROM cell which is placed on an intersection point of the word-line and the bit-line, to program a datum into the EPROM cell by using a high power supply voltage when the decoder circuit operates under a programming mode and to read out a datum stored in the EPROM cell by using a low power supply voltage when the decoder circuit operates under a reading mode, receiving an address signal from the exterior of the decoder circuit. The decoder circuit comprises a NAND gate having its load and a CMOS invertor. In making the load of the NAND gate function as a constant current load, only a variable power supply voltage, which becomes a high and a low voltage according to the programming and the reading mode respectively, can be applied to the decoder circuit without using other elements such as a transfer gate and a compensator as required in the prior art.
Inventors
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:35
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/08; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
185 words
A decoder circuit connected to a variable power supply source to receive a variable power supply voltage having one of first and second power supply voltage levels selectively, for decoding address signals and providing a selection signal of said first or second power supply voltage level respectively, said decoder circuit comprising: a decoding logic gate, for decoding the address signals supplied to said decoding logic gate and having an output to provide a decoded signal, said decoding logic gate having a constant current load with comprises a depletion transistor having a gate, a source connected to said gate, and providing an output therefrom, and a drain connected to said variable power supply source; said decoding logic gate further including a plurality of input transistors, connected in series to said constant current load for receiving said address signals, such that said series connected input transistors form a NAND gate; and an output circuit, connected to said variable power supply source and to said output of said decoding logic gate for receiving said decoded signal, and for providing said selection signal in response to said decoded signal.
Claim 2
Dependent Claim
185 words
A decoder circuit connected to a variable power supply source to receive a variable power supply voltage having one of first and second power supply voltage levels selectively, for decoding address signals and providing a selection signal of said first or second power supply voltage level respectively, said decoder circuit comprising: a decoding logic gate, for decoding the address signals supplied to said decoding logic gate and having an output to provide a decoded signal, said decoding logic gate having a constant current load with comprises a depletion transistor having a gate, a source connected to said gate, and providing an output therefrom, and a drain connected to said variable power supply source; said decoding logic gate further including a plurality of input transistors, connected in series to said constant current load for receiving said address signals, such that said series connected input transistors form a NAND gate; and an output circuit, connected to said variable power supply source and to said output of said decoding logic gate for receiving said decoded signal, and for providing said selection signal in response to said decoded signal.
Claim 3
Dependent Claim
14 words
A decoder circuit according to claim 1, wherein said output circuit comprises an inverter.
Claim 4
Dependent Claim
126 words
A decoder circuit according to claim 2, wherein said inverter is a CMOS (Complimentary Metal Oxide Semiconductor) inverter comprising a p channel type transistor and an n channel type transistor connected in series such that the source of the p channel type transistor is connected to the drain of said n channel type transistor for providing an output of said selection signal therefrom, and wherein the drain of the p channel type transistor is connected to said variable power supply voltage and the source of the n channel type transistor is connected to earth potential, each of said p channel and n channel type transistors having a commonly connected gate which is connected to the output of said decoding logic gate to receive said decoded signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-01 | 1992-05-02 | 1992-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-01 | 1996-05-02 | 1996-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-01 | 2000-05-02 | 2000-11-01 | $7700.00 | Window Closed / Lapsed |