EP0060078A2
Expired / Lapsed
EP
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Read-only memory device
Assignee: Fujitsu Ltd
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Filing: 1982-03-02
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Granted: —
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Expires: 2002-03-02
Abstract
Abstract A read-only memoy device comprises a plurality of groups of bit lines (BL o , BL,,..., BL 63 ). One bit line within each group is selected by first column address decoders (4-1) and one group is selected by second column address decoders (8-0 - 8-3). One load element (Q L0 , Q L1 ,Q L2 , Q L3 ) is provided in each second column address decoder so as to pull up the potentials of the bit lines.
Inventors
- 👤 Yasuo C/O Azuma Suzuki
- 👤 Hiroshi Hirao
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 11:48
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/24; G11C17/14; G11C17/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
194 words
A read-only memory device comprising: first and second power supplies; a plurality of word lines; a plurality of groups of bit lines; a plurality of read-only memory cells located at intersections between said word lines and said bit lines; a plurality of data bus lines, the number of which is the same as that of said groups of bit lines; a plurality of groups of switching gates, each group of switching gates being connected between one of said groups of bit lines and one of said data bus lines; a plurality of first column decoders, connected to said switching gates, for selecting one switching gate within each group of switching gates in accordance with a first column address information, so as to turn on the selected switching gate; a plurality of second column decoders, each connected to said first and second power supplies and to one of said data bus lines, for selecting one of said data bus lines in accordance with a second column address information, so as to charge the selected data bus line; a sense amplifier connected to said data bus lines; and an output buffer connected to said sense amplifier.
Claim 2
Dependent Claim
194 words
A read-only memory device comprising: first and second power supplies; a plurality of word lines; a plurality of groups of bit lines; a plurality of read-only memory cells located at intersections between said word lines and said bit lines; a plurality of data bus lines, the number of which is the same as that of said groups of bit lines; a plurality of groups of switching gates, each group of switching gates being connected between one of said groups of bit lines and one of said data bus lines; a plurality of first column decoders, connected to said switching gates, for selecting one switching gate within each group of switching gates in accordance with a first column address information, so as to turn on the selected switching gate; a plurality of second column decoders, each connected to said first and second power supplies and to one of said data bus lines, for selecting one of said data bus lines in accordance with a second column address information, so as to charge the selected data bus line; a sense amplifier connected to said data bus lines; and an output buffer connected to said sense amplifier.
Claim 3
Dependent Claim
74 words
A device as set forth in claim 1, wherein each of said second column decoders comprises: an AND circuit, operatively connected to said first power supply and to one of said data bus lines, for receiving one combination of said second column address information; and a first NOR circuit, connected to said AND circuit and to said second power supply, for receiving the inverted information of said one combination of said second column information.
Claim 4
Dependent Claim
45 words
A device as set forth in claim 2, wherein each of said second column decoders further comprises a first load element connected between said first power supply and said AND circuit, said first load element comprising a depletion type source-gate connected metal-insulated semiconductor (MIS) transistor.
Claim 5
Dependent Claim
33 words
A device as set forth in claim 3, wherein said AND circuit comprises a plurality of MIS transistors connected in series having gates for receiving the combination of said second column address information.
Claim 6
Dependent Claim
39 words
A device as set forth in claim 3, wherein said first NOR circuit comprises a plurality of MIS transistors connected in parallel having gates for receiving the inverted information of said one combination of said second column address information.
Claim 7
Dependent Claim
51 words
A device as set forth in claim 2, wherein said sense amplifier comprises: a second load element connected to said first power supply; and a second NOR circuit connected to said load element and to said second power supply and having gates for receiving the potentials of said data bus lines.
Claim 8
Dependent Claim
22 words
A device as set forth in claim 6, wherein said second NOR circuit comprises a plurality of MIS transistors connected in parallel.
Claim 9
Independent Claim
94 words
A device as set forth in claim I, wherein each of said second column decoders comprises: a plurality of MIS transistors of a first conductivity type connected in series between said first power supply and one of said data bus lines and having gates for receiving one combination of said second column address information; and a plurality of MIS transistors of a second conductivity type connected in parallel between said first power supply and one of said data bus lines and having gates for receiving said one combination of said second column address information.
Claim 10
Dependent Claim
82 words
A device as set forth in claim 8, wherein said sense amplifier comprises: a plurality of MIS transistors of said first conductivity type connected in series between said first power supply and said output buffer and having gates for receiving the potentials of said data bus lines; and a plurality of MIS transitors of said second conductivity type connected in parallel between said second power supply and said output buffer and having gates for receiving the potentials of said data bus lines.
References Cited (Backward Citations)
No citation records indexed.
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