Buried interconnect for silicon on insulator structure

Claim 2

In a metal-oxide-semiconductor (MOS) structure comprising a semiconductor substrate, an insulative layer formed over said semiconductor substrate, and a semiconductor layer formed over said insulative layer, a process for forming an interconnect in said semiconductor substrate between first and second devices formed in said semiconductor layer, said process comprising the steps of: forming a doped region in said semiconductor substrate prior to forming said insulative layer on said substrate; forming a second opening distinct from said first opening through said insulative layer over a second portion of said doped region; forming said semiconductor layer over said insulative layer; forming one of a source and drain terminal of said first device in said semiconductor layer over said first opening; and forming a terminal of said second device in said semiconductor layer over said second opening such that said doped region provides said interconnect in said substrate for interconnecting said terminals of each of said first and second devices.

Claim 3

The process of claim 1 further comprising the step of forming insulative regions in said semiconductor substrate adjacent to said doped region after forming said doped region and prior to forming said insulative layer.

Claim 4

The process of claim 1, wherein said semiconductor substrate comprises a silicon substrate and said insulative regions in said substrate adjacent to said doped region remain by: forming a silicon nitride member over at least a portion of said doped region; growing an oxide layer on said substrate with said silicon nitride member in place; removing said silicon nitride member; and etching said oxide layer such that said doped region is exposed at the site of said removed silicon nitride member, and said insulative regions remain adjacent to said site of said removed silicon nitride member.

Claim 5

The process of claim 3 wherein said semiconductor layer comprises a polysilicon layer which is recrystallized.

Claim 6

The process of claim 1 wherein said insulative layer comprises a silicon dioxide layer.

Claim 7

The process of claim 1 wherein said terminal of said second device comprises one of a source and drain of said second device.

Claim 8

In a metal-oxide-semiconductor (MOS) structure comprising a semiconductor substrate, an insulative layer formed over said substrate, and a semiconductor layer formed over said insulative layer, a process for forming interconnects in said substrate below said insulative layer for interconnecting a plurality of devices formed in said semiconductor layer, said process comprising the steps of: forming doped regions in said substrate prior to forming said insulative layer on said substrate, each of said doped regions for interconnecting terminals of a predetermined number of said devices; forming said insulative layer over said substrate; forming an opening through said insulative layer over each of said doped regions for each of said predetermined number of devices; forming said semiconductor layer over said insulative layer; forming one of said terminals of each of said predetermined number of devices at each one of said openings such that said doped regions disposed in said substrate provide interconnects in said substrate among said terminals, each of said terminals being one of source and drain of each of said devices.

Claim 9

In a metal-oxide-semiconductor (MOS) structure comprising a semiconductor substrate, an insulative layer formed over said substrate, and a semiconductor layer formed over said insulative layer, a process for forming interconnects in said substrate below said insulative layer for interconnecting a plurality of devices formed in said semiconductor layer, said process comprising the steps of: forming doped regions in said substrate prior to forming said insulative layer on said substrate, each of said doped regions for interconnecting terminals of a predetermined number of said devices; forming said insulative layer over said substrate; forming an opening through said insulative layer over each of said doped regions for each of said predetermined number of devices; forming said semiconductor layer over said insulative layer; forming one of said terminals of each of said predetermined number of devices at each one of said openings such that said doped regions disposed in said substrate provide interconnects in said substrate among said terminals, each of said terminals being one of source and drain of each of said devices.

Claim 10

The process of claim 7 further comprising the step of forming insulative regions in said substrate adjacent to said doped regions after forming said doped regions and prior to forming said insulative layer.

Claim 11

The process of claim 8 wherein said semiconductor substrate comprises a silicon substrate and said insulative regions in said substrate adjacent to said doped regions remain by: forming silicon nitride members over predetermined portions of said doped regions; growing an oxide layer on said substrate with said silicon nitride members in place; removing said silicon nitride members; and etching said oxide layer such that said doped regions are exposed at the sites of said removed silicon nitride members and said insulative regions remain adjacent to said sites of said removed silicon nitride members.

Claim 12

The process of claim 9 wherein said semiconductor layer comprises a polysilicon layer recrystallized over said openings in said insulative layer.

Claim 13

The process of claim 10 wherein said insulative layer comprises a silicon dioxide layer.

Claim 14

The process of claim 11 wherein said semiconductor substrate comprises a silicon substrate.