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US4777718A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming and connecting a resistive layer on a pc board

Assignee: Motorola Solutions Inc
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Filing: 1986-06-30
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Granted: 1988-10-18
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Expires: 2006-06-30
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Abstract

Abstract A resistive element is formed on a printed circuit board using only printed circuit board fabrication techniques. A substrate having a bi-metallic cladding on one side of the substrate and a conductive metallic cladding on an opposing side of the substrate is used. A predetermined trace pattern is formed in the metallic cladding. Resistive elements are formed in the bi-metallic cladding opposing their desired locations in the trace pattern. The bi-metallic cladding consists of a resistive layer between the substrate and a second conductive layer. Tabs are etched in the second conductive layer, then resistors, which couple various tabs together, are etched in the resistive layer. Plated holes connect the tabs to desired locations in the trace pattern located on the opposing side of the substrate.

Inventors

  • 👤 James M. Henderson
  • 👤 Ronald F. Kielmeyer, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 21:02
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/16; H05K1/167; H01; H01C; H01C17/00; H01C17/06; H01C17/07; H01Q; H01Q21/00; H01Q21/0006; H01Q21/0075; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0355; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09254; H05K2201/095; H05K2201/09536; H05K2203/00; H05K2203/03; H05K2203/0361; H05K3/00; H05K3/02; H05K3/06; H05K3/40; H05K3/42; H05K3/425; H05K3/427; H05K3/46; H05K3/4644; H05K3/4652; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49099; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49155; Y10T29/49165

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 325 words
A method of fabricating a resistor on a printed circuit board having a first conductive layer contacting a first side of a dielectric substrate, a first side of a resistive metal layer contacting a second side of the dielectric substrate, and a second conductive layer contacting a second side of the resistive metal layer, said method comprising the steps of: forming first and second traces from the first conductive layer, the first and second traces each having a coupling section; forming first and second pads from the second conductive layer, the first and second pads opposing the coupling sections of the first and second traces, respectively; making a first hole through the coupling section of the first trace, the substrate, the resistive layer, and the first tab to provide a first hole wall; making a second hole through the coupling section of the second trace, the substrate, the resistive layer, and the second tab to provide a second hole wall; plating the first and second hole walls so that first and second conductive paths form between the first pad and first trace and between the second pad and second trace, respectively; removing portions of the resistive metal layer which do not reside between the first and second pads; bonding a second printed circuit board, having a dielectric substrate with first and second substantially parallel sides and having a conductive layer contacting the first side of the second circuit board substrate, to the printed circuit so that the second side of the second printed circuit substrate resides adjacent to the second side of the printed circuit substrate; and bonding a third printed circuit board, having a dielectric substrate with first and second substantially parallel sides and having a conductive layer contacting the first side of the third circuit board substrate, to the printed circuit so that the second side of the third circuit board substrate resides adjacent to the first side of the printed circuit substrate.
Claim 2
Independent Claim 325 words
A method of fabricating a resistor on a printed circuit board having a first conductive layer contacting a first side of a dielectric substrate, a first side of a resistive metal layer contacting a second side of the dielectric substrate, and a second conductive layer contacting a second side of the resistive metal layer, said method comprising the steps of: forming first and second traces from the first conductive layer, the first and second traces each having a coupling section; forming first and second pads from the second conductive layer, the first and second pads opposing the coupling sections of the first and second traces, respectively; making a first hole through the coupling section of the first trace, the substrate, the resistive layer, and the first tab to provide a first hole wall; making a second hole through the coupling section of the second trace, the substrate, the resistive layer, and the second tab to provide a second hole wall; plating the first and second hole walls so that first and second conductive paths form between the first pad and first trace and between the second pad and second trace, respectively; removing portions of the resistive metal layer which do not reside between the first and second pads; bonding a second printed circuit board, having a dielectric substrate with first and second substantially parallel sides and having a conductive layer contacting the first side of the second circuit board substrate, to the printed circuit so that the second side of the second printed circuit substrate resides adjacent to the second side of the printed circuit substrate; and bonding a third printed circuit board, having a dielectric substrate with first and second substantially parallel sides and having a conductive layer contacting the first side of the third circuit board substrate, to the printed circuit so that the second side of the third circuit board substrate resides adjacent to the first side of the printed circuit substrate.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-10-18 1992-04-18 1992-10-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-10-18 1996-04-18 1996-10-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-10-18 2000-04-18 2000-10-18 $7700.00 Window Closed / Lapsed

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