Differential circuit

Claim 2

A differential circuit, coupled to a low voltage power source and a high voltage power source, comprising: a first drive FET and a second drive FET each having a gate connected to an input, having a drain, and having a source, the sources of said first drive FET and said second drive FET being commonly connected at a node; a constant current FET connected between the node and the low voltage power source; a first load circuit provided between the drain of said first drive FET and the high voltage power source; a second load circuit provided between the drain of said second drive FET and the high voltage power source; each of said first and second load circuits being formed by a first load FET having a drain connected to the high voltage power source, and having a gate and a source which are short-circuited and connected to the drain of the corresponding one of said first and second drive FETs, and a second load FET having a drain connected to the high voltage power source, having a source connected to the dran of the corresponding one of said first and second drive FETs and having a gate with a constant voltage applied thereto; and output terminals connected to the drains of said first drive FET and said second drive FET, respectively.

Claim 3

A differential circuit according to claim 1, wherein said first load FET, said second load FET, and said constant current FET have a substantially equal K value and V th , and wherein the sum of gate widths of said first load FET and said second load FET is substantially equal to a gate width of said constant current FET.

Claim 4

A differential circuit according to claim 1, wherein said FET's are formed by a MESFET.

Claim 5

An integrated circuit device comprising: a high voltage power source; a low voltage power source; an intermediate voltage power source between said high voltage power source and said low voltage power source; input terminals; a converter circuit coupled to said input terminals, including: first and second drive FETs, each having a gate connected to a corresponding one of said input terminals, having a drain and having a source, the sources of said first drive FET and said second drive FET being commonly connected at a node; a constant current FET connected between the node and said low voltage power source; a first load circuit provided between the drain of said first drive FET and said high voltage power source; a second load circuit provided between the drain of said second drive FET and said high voltage power source; each of said first and second load circuits being formed by a first load FET having a drain connected to said high voltage power source, and having a gate and a source which are short-circuited and connected to the drain of the corresponding one of said first and second drive FETs, and a second load FET having a drain connected to said high voltage power source, having a source connected to the drain of the corresponding one of said first and second drive FETs and having a gate with said intermediate voltage applied thereto; output terminals connected to the drains of said first drive FET and said second drive FET; an internal circuit provided between said high voltage power source and said intermediate voltage power source and having a third load FET and a third drive FET in series, and of said output terminals of said converter circuit being connected to the gate of said third drive FET in said internal circuit.

Claim 6

An integrated circuit device comprising: a high voltage power source; a low voltage power source; an intermediate voltage power source between said high voltage power source and said low voltage power source; input terminals; a converter circuit coupled to said input terminals, including: first and second drive FETs, each having a gate connected to a corresponding one of said input terminals, having a drain and having a source, the sources of said first drive FET and said second drive FET being commonly connected at a node; a constant current FET connected between the node and said low voltage power source; a first load circuit provided between the drain of said first drive FET and said high voltage power source; a second load circuit provided between the drain of said second drive FET and said high voltage power source; each of said first and second load circuits being formed by a first load FET having a drain connected to said high voltage power source, and having a gate and a source which are short-circuited and connected to the drain of the corresponding one of said first and second drive FETs, and a second load FET having a drain connected to said high voltage power source, having a source connected to the drain of the corresponding one of said first and second drive FETs and having a gate with said intermediate voltage applied thereto; output terminals connected to the drains of said first drive FET and said second drive FET; an internal circuit provided between said high voltage power source and said intermediate voltage power source and having a third load FET and a third drive FET in series, and of said output terminals of said converter circuit being connected to the gate of said third drive FET in said internal circuit.

Claim 7

An integrated circuit device according to claim 4, further comprising a level shift circuit provided between the output terminals of said converter circuit and the gate of said third drive FET of said internal circuit.

Claim 8

An integrated circuit device according to claim 5, wherein the input terminals are coupled to receive ECL level signals, and wherein said internal circuit is a GaAs BFL internal circuit.

Claim 9

An integrated circuit device according to claim 4, wherein the input terminals are coupled to receive ECL level signals, and wherein said internal circuit is a GaAs DCFL internal circuit.