High gain mos linear integrated circuit amplifier

Claim 2

A signal amplifying circuit comprising: amplifying means comprising a first semiconductor amplifying device having input, output, and common electrodes; means for coupling input signals between said common and said input electrode; and output load means across which output signals corresponding to amplified input signals are produced, said output load means being coupled between said output electrode and a supply terminal adapted for connection to a source of voltage and comprising: a second semiconductor device having a relatively high impedance; a third semiconductor device for providing an auxiliary conduction path; means coupling said third semiconductor device between said output electrode and said supply terminal; and biasing means coupled to said third semiconductor device for coupling said second high impedance semiconductor device in parallel with said third semiconductor device and for biasing said third semiconductor device to substantially constant current operation over a predetermined range of said input signals.

Claim 3

A signal amplifying circuIt according to claim 1 wherein each of said semiconductor devices is a field-effect transistor having a source electrode, a drain electrode and a gate electrode.

Claim 4

A signal amplifying circuit according to claim 2 wherein said input, output, and common electrodes correspond respectively to gate, drain, and source electrodes of said amplifying device; said auxiliary conduction path corresponds to the source-drain path of said third semiconductor load device; and said biasing means is coupled between the gate and source of said third load device.

Claim 5

A signal amplifying circuit according to claim 3 wherein said drain and gate electrodes of said second device are directly connected together.

Claim 6

A signal amplifying circuit according to claim 4 wherein said biasing means comprises at least one additional field-effect transistor having drain and gate electrodes connected directly together and to the gate of said third semiconductor device, and a source electrode connected to the source of said third semiconductor device.

Claim 7

A signal amplifying circuit according to claim 4 wherein said biasing means comprises a plurality of field-effect transistors each having source, gate, and drain electrodes, the gate and drain electrodes being connected together, the connected gate-drain of a first of said transistors being connected to the gate of said third semiconductor device and the source electrode of a last of said transistors being connected to the source of said third semiconductor device, the source electrode of said first and succeeding transistors other than said last being connected to the connected gate and drain electrodes of a next succeeding transistor.

Claim 8

A signal amplifying circuit according to claim 6 wherein said plurality of field-effect transistors are connected in series with said second semiconductor device for biasing said third semiconductor device to substantially constant current operation.

Claim 9

A signal amplifying circuit according to claim 7 wherein said field-effect transistors are enhancement type, insulated gate, metal-oxide semiconductor field-effect transistors.

Claim 10

A signal amplifying circuit comprising: amplifying means comprising a first metal-oxide semiconductor field-effect transistor having source, gate and drain electrodes; means for coupling input signals between said source and said gate electrode; and output load means across which output signals corresponding to amplified input signals are produced, said output load means being coupled between said drain electrode and a supply terminal adapted for connection to a source of voltage and comprising: a second metal-oxide semiconductor field-effect transistor having source, drain and gate electrodes for providing a relatively high impedance, a third metal-oxide semiconductor field-effect transistor having source, gate, and drain electrodes for providing an auxiliary conduction path, means coupling said source and drain of said third field-effect transistor between said drain electrode of said first field-effect transistor and said supply terminal; and biasing means coupled to said gate and source of said third field-effect transistor for coupling said source and drain of said second field-effect transistor in parallel with said source and drain of said third field-effect transistor and for biasing said gate and drain of said third field-effect transistor to produce substantially constant source-drain current operation of said third transistor over a predetermined range of said input signals.

Claim 11

A signal amplifying circuit comprising: amplifying means comprising a first metal-oxide semiconductor field-effect transistor having source, gate and drain electrodes; means for coupling input signals between said source and said gate electrode; and output load means across which output signals corresponding to amplified input signals are produced, said output load means being coupled between said drain electrode and a supply terminal adapted for connection to a source of voltage and comprising: a second metal-oxide semiconductor field-effect transistor having source, drain and gate electrodes for providing a relatively high impedance, a third metal-oxide semiconductor field-effect transistor having source, gate, and drain electrodes for providing an auxiliary conduction path, means coupling said source and drain of said third field-effect transistor between said drain electrode of said first field-effect transistor and said supply terminal; and biasing means coupled to said gate and source of said third field-effect transistor for coupling said source and drain of said second field-effect transistor in parallel with said source and drain of said third field-effect transistor and for biasing said gate and drain of said third field-effect transistor to produce substantially constant source-drain current operation of said third transistor over a predetermined range of said input signals.

Claim 12

A signal amplifying circuit according to claim 9 wherein said biasing means comprises a field-effect transistor having source, drain, and gate electrodes, said gate and drain electrodes being connected together and coupled in a series path including said second field-effect transistor between said supply terminal and the drain electrode of said first field-effect transistor.

Claim 13

A signal amplifying circuit according to claim 10 wherein said gate aNd drain electrodes of said second field-effect transistor are connected together and coupled to the drain electrode of said third field-effect transistor and to said supply terminal, the gate of said third field-effect transistor being coupled to the junction of the source electrode of said second field-effect transistor and the drain electrode of said fourth field-effect transistor connected in series, the source electrode of said third field-effect transistor being coupled to the drain electrode of said first electrode.

Claim 14

A signal amplifying circuit according to claim 11 wherin said biasing means comprises a plurality of field-effect transistors, each having source, gate, and drain electrodes, the gate and drain electrodes being connected together, the connected gate-drain of a first of said transistors being connected to the gate of said third field-effect transistor and the source electrode of a last of said field-effect transistors being connected to the source of said third field-effect transistor, the source electrode of said first and succeeding field-effect transistors other than said last being connected to the connected gate and drain electrodes of a next succeeding transistor.