Patent US4775931A successfully refreshed from Google Patents.
US4775931A
Expired / Lapsed
US
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Dynamically configured computing device
Assignee: HP Inc
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Filing: 1987-04-02
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Granted: 1988-10-04
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Expires: 2007-04-02
Abstract
Abstract A computing system is presented which has a central processing unit (CPU) and peripheral devices. Identification registers associated with each peripheral device may be accessed by the CPU to identify characteristics of individual peripheral devices. Additionally, configuration registers within each peripheral device allow a particular peripheral device to determine whether instructions from the CPU are addressing that particular peripheral device.
Inventors
- 👤 James P. Dickie
- 👤 David M. Rabinowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4411; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
323 words
A computing device comprising: CPU means for processing data; a first peripheral device coupled to the CPU means, the first peripheral device including a first plurality of memory locations which serve as directly addressable memory for the CPU means, and first configuration register means, coupled to the first plurality of memory locations, for storing bits which serve as high order bits of addresses for the memory locations within the first plurality of memory locations; identification register means coupled to the first peripheral device for storing data identifying characteristics of the first peripheral device, wherein the first peripheral device provides the CPU means with data from the identification register means in order to identify to the CPU means the amount of memory locations within the first plurality of memory locations; a second peripheral device coupled to the CPU means, the second peripheral device comprising a second plurality of memory locations which serve as directly addressable memory for the CPU, and second configuration register means coupled to the second plurality of memory locations for storing bits which serve as high order bits of addresses for the memory locations within the second plurality of memory locations; and, daisy-chain means coupled to the CPU, the first peripheral device, and the second peripheral device for allowing the CPU to separately initialize the first configuration register means and the second configuration register means, the second peripheral device having a daisy-chain input line connected to a daisy-chain output line of the first peripheral device, and a daisy-chain input line of the first peripheral device being connected to the CPU means, wherein the first peripheral device includes flag means responsive to command from said CPU means for indicating that the first peripheral device is configured and wherein the first peripheral device includes means for changing a signal on the daisy-chain output line of the first peripheral device based on a signal on the daisy-chain input line of the first peripheral device.
Claim 2
Dependent Claim
323 words
A computing device comprising: CPU means for processing data; a first peripheral device coupled to the CPU means, the first peripheral device including a first plurality of memory locations which serve as directly addressable memory for the CPU means, and first configuration register means, coupled to the first plurality of memory locations, for storing bits which serve as high order bits of addresses for the memory locations within the first plurality of memory locations; identification register means coupled to the first peripheral device for storing data identifying characteristics of the first peripheral device, wherein the first peripheral device provides the CPU means with data from the identification register means in order to identify to the CPU means the amount of memory locations within the first plurality of memory locations; a second peripheral device coupled to the CPU means, the second peripheral device comprising a second plurality of memory locations which serve as directly addressable memory for the CPU, and second configuration register means coupled to the second plurality of memory locations for storing bits which serve as high order bits of addresses for the memory locations within the second plurality of memory locations; and, daisy-chain means coupled to the CPU, the first peripheral device, and the second peripheral device for allowing the CPU to separately initialize the first configuration register means and the second configuration register means, the second peripheral device having a daisy-chain input line connected to a daisy-chain output line of the first peripheral device, and a daisy-chain input line of the first peripheral device being connected to the CPU means, wherein the first peripheral device includes flag means responsive to command from said CPU means for indicating that the first peripheral device is configured and wherein the first peripheral device includes means for changing a signal on the daisy-chain output line of the first peripheral device based on a signal on the daisy-chain input line of the first peripheral device.
Claim 3
Dependent Claim
64 words
A computing device as in claim 1 wherein the high order bits stored in the first configuration register means in the first peripheral device define a first address space, wherein the high order bits stored in the second configuration means in the second peripheral device define a second address space, and wherein the first address space is not equal to the second address space.
Claim 4
Dependent Claim
63 words
A computing device as in claim 2 wherein the first peripheral device additionally comprises: data pointer register means for storing a third address to which the CPU means requests access, wherein the first peripheral device compares contents of the first configuration register means with high order bits from the third address to determine whether the address addresses memory within the first address space.
Claim 5
Dependent Claim
318 words
In a computing system having a central processing unit, a first peripheral device having a first plurality of memory locations directly addressable by the central processing device and a second peripheral device having a second plurality of memory locations directly addressable by the central processing device, wherein the second peripheral device has a daisy-chain input line connected to a daisy-chain output line of the first peripheral device and a daisy-chain input line of the first peripheral device is connected to the central processing unit, a method by which the central processing unit assigns addresses to the first plurality of memory locations within the first peripheral device and the second peripheral device, the method comprising: examining contents of an identification register within the first peripheral device by the central processing unit to determine the amount of memory locations within the first peripheral device; transferring to the first peripheral device a first configuration address which indicates the address of the first peripheral device in the computing system address space; storing high order bits of the first configuration address to identify the high order bits of the address of each memory location in the first plurality of memory locations; examining contents of an identification register within the second peripheral device by the central processing unit to determine the amount of memory locations within the second peripheral device; transferring to the second peripheral device a second configuration address which indicates the address of the second peripheral device in the computing system address space; storing high order bits of the second configuration address to identify the high order bits of the address of each memory location in the second plurality of memory locations; indicating with a flag that the first peripheral device has been configured; and changing a signal on the daisy-chain output line of the first peripheral device based on a signal on the daisy-chain input line of the first peripheral device.
Claim 6
Dependent Claim
318 words
In a computing system having a central processing unit, a first peripheral device having a first plurality of memory locations directly addressable by the central processing device and a second peripheral device having a second plurality of memory locations directly addressable by the central processing device, wherein the second peripheral device has a daisy-chain input line connected to a daisy-chain output line of the first peripheral device and a daisy-chain input line of the first peripheral device is connected to the central processing unit, a method by which the central processing unit assigns addresses to the first plurality of memory locations within the first peripheral device and the second peripheral device, the method comprising: examining contents of an identification register within the first peripheral device by the central processing unit to determine the amount of memory locations within the first peripheral device; transferring to the first peripheral device a first configuration address which indicates the address of the first peripheral device in the computing system address space; storing high order bits of the first configuration address to identify the high order bits of the address of each memory location in the first plurality of memory locations; examining contents of an identification register within the second peripheral device by the central processing unit to determine the amount of memory locations within the second peripheral device; transferring to the second peripheral device a second configuration address which indicates the address of the second peripheral device in the computing system address space; storing high order bits of the second configuration address to identify the high order bits of the address of each memory location in the second plurality of memory locations; indicating with a flag that the first peripheral device has been configured; and changing a signal on the daisy-chain output line of the first peripheral device based on a signal on the daisy-chain input line of the first peripheral device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-04 | 1992-04-04 | 1992-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-04 | 1996-04-04 | 1996-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-04 | 2000-04-04 | 2000-10-04 | $7700.00 | Window Closed / Lapsed |