US4556953A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interchangeable interface circuitry arrangements for use with a data processing system
Assignee: Compaq Information Technologies Group LP
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Filing: 1982-02-24
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Granted: 1985-12-03
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Expires: 2002-02-24
Abstract
Abstract The present disclosure is directed to an arrangement whereby any one of a plurality of different or similar interface circuit cards can be located into any one of a number of slots or holding means of a data processing system, without preassignment thereto, and whereby each of the interface circuit cards will generate its own diagnostic routine signals and signals representing its own identification, the latter signals being used in a self-configuration operation of the system and whereby an arbiter means is employed to determine, among the plurality of interface circuits, which has the highest priority in the event more than one of said interface circuits is requesting the use of a common data flow path.
Inventors
- 👤 A. Ronald Caprio
- 👤 John P. Cyr
- 👤 Bernard O. Geaghan
- 👤 Paul C. Kotschenreuther
- 👤 David J. Schanin
- 👤 Ronald M. Salett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F11/00; G06F11/22; G06F11/2289; G06F11/006; G06F11/26; G06F11/273; G06F11/277; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F13/14; G06F13/20; G06F13/28; G06F13/30; G06F13/36; G06F13/368; G06F13/374; G05; G05B; G05B2219/00; G05B2219/20; G05B2219/25; G05B2219/25092
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
358 words
In association with a data processing system, which includes central processor circuitry means, memory circuitry means holding at least address signals, control logic circuitry means and bus circuitry interconnecting the three last mentioned circuitry means, means for enabling said data processing system to interchangeably utilize any one of a plurality of data signal responsive means, said means for enabling comprising in combination: a plurality of circuit mounting means, each having at least one interface circuit mounted thereon; a plurality of holding means with each having first engageable electrical terminals with said each first engageable terminal having an engageable end and a non-engageable end with said non-engageable end connected to said bus circuitry and with at least one of said terminals being designated an address terminal; first circuitry coupled through said bus circuitry to said memory circuitry means and formed to receive and decode sets of address signals from said memory circuitry means and wherein each set of address signals designates a different one of said address terminals; second circuitry means connected to respectively transmit decoded address signals from said first circuitry through said bus circuitry to associated ones of said address terminals whereby each of said address terminals will be respectively activated in response to its address signals being decoded; a plurality of interface circuitry means with each having second engaging electrical terminals and each of said interface circuitry means located on a different one of said circuit mounting means and each further in engaging relationship with said first engageable terminals of an associated holding means to be thereby connected to said bus circuitry and each interface circuitry means connected to an associated one of said data signal responsive means, and each interface circuitry means further providing identifying signals; instruction circuitry means coupled through said bus circuitry means to said memory circuitry means to provide signals to cause said memory circuitry means to store at an address, determined in part by a set of said identifying signals, a set of said address signals which when decoded represent the address terminal of said holding means whereat the one of said interface circuitry means providing said identifying signals is located.
Claim 2
Dependent Claim
358 words
In association with a data processing system, which includes central processor circuitry means, memory circuitry means holding at least address signals, control logic circuitry means and bus circuitry interconnecting the three last mentioned circuitry means, means for enabling said data processing system to interchangeably utilize any one of a plurality of data signal responsive means, said means for enabling comprising in combination: a plurality of circuit mounting means, each having at least one interface circuit mounted thereon; a plurality of holding means with each having first engageable electrical terminals with said each first engageable terminal having an engageable end and a non-engageable end with said non-engageable end connected to said bus circuitry and with at least one of said terminals being designated an address terminal; first circuitry coupled through said bus circuitry to said memory circuitry means and formed to receive and decode sets of address signals from said memory circuitry means and wherein each set of address signals designates a different one of said address terminals; second circuitry means connected to respectively transmit decoded address signals from said first circuitry through said bus circuitry to associated ones of said address terminals whereby each of said address terminals will be respectively activated in response to its address signals being decoded; a plurality of interface circuitry means with each having second engaging electrical terminals and each of said interface circuitry means located on a different one of said circuit mounting means and each further in engaging relationship with said first engageable terminals of an associated holding means to be thereby connected to said bus circuitry and each interface circuitry means connected to an associated one of said data signal responsive means, and each interface circuitry means further providing identifying signals; instruction circuitry means coupled through said bus circuitry means to said memory circuitry means to provide signals to cause said memory circuitry means to store at an address, determined in part by a set of said identifying signals, a set of said address signals which when decoded represent the address terminal of said holding means whereat the one of said interface circuitry means providing said identifying signals is located.
Claim 3
Dependent Claim
110 words
In association with said data processing system and said means for enabling according to claim 1, wherein said data processing means has at least one main data flow path which can be used by various ones of said interface circuitry means in the course of operation and wherein at least two of said interface circuitry means are formed to each have different priority determination circuitry and wherein said priority determination circuitries are connected together and are formed to determine if one of said at least two interface circuitry means has a higher priority to enable such interface circuitry means to be temporarily in control of said main data flow path.
Claim 4
Dependent Claim
104 words
In association with said data processing system and said means for enabling according to claim 2, wherein with respect to said at least two interface circuitry means each has an assigned priority value, and wherein there is further included arbitor circuitry means coupled to said at least two priority determining circuitry means and formed to determine which of said at least two interface circuitry means has the higher priority in order to be temporarily in control of said main data flow path in the event that said priority determination circuitry determines that said at least two interface circuitry means have the same priority value.
Claim 5
Dependent Claim
106 words
In association with said data processing system and said means for enabling according to claim 2, wherein each of said interface circuitry means has a priority value and each of said priority determination circuitries is formed to generate a demand for control signal, and wherein there is further included a "last look" circuit, which is formed to prevent an interface circuitry means from taking control of said main data flow path after said demand for control signal has been generated, in the event that an interface circuitry means of higher priority generates a demand for control signal to take control of said main data flow path.
Claim 6
Dependent Claim
77 words
In association with said data processing system and said means for enabling according to claim 4, wherein said "last look" circuit is further formed to continually monitor the demand for control signals and formed to block an interface circuitry means from controlling said main data flow path, even after said control has been granted to said last mentioned interface circuitry means, in the event an interface circuitry means having high priority generates a demand for control signal.
Claim 7
Dependent Claim
65 words
In association with said data processing system and said means for enabling according to claim 2, wherein there is further included a programmable means as part of said priority determination circuitry whereby said priority determination circuitry can generate a priority value for the interface circuit of which it is made a part in accordance with program generated input signals transmitted to said priority determination circuitry.
Claim 8
Dependent Claim
113 words
In association with said data processing system and said means for enabling according to claim 1, the further inclusion, as part of each interface circuitry means, a diagnostic memory circuitry means which is formed to have a diagnostic routine stored therein, which routine is particularly directed to the interface circuitry means of which it is a part, and wherein said each diagnostic memory circuitry means is formed to provide instruction data signals to said data processing means whereby said data processing means can cause certain different tests to be performed respectively on each of said interface circuitry means in accordance with said instruction data signals provided by each said diagnostic memory circuitry means.
Claim 9
Dependent Claim
92 words
In association with said data processing system and said means for enabling according, to claim 1, the further inclusion of a plurality of option present circuits, wherein at least one different one of said option present circuits is associated with a different holding means and is activated when one of said interface circuitry means is engaged with its associated holding means and the further inclusion of register means connected to said option present circuits to provide signals to said data processing system to indicate which of said interface circuitry means is present.
References Cited (Backward Citations)
US3102767A
Cited
US3848233A
Cited
US4130865A
Cited
US4001790A
Cited
US4025906A
Cited
US4124888A
Cited
US3997879A
Cited
US4171541A
Cited
US4271465A
Cited
US4155115A
Cited
US4223380A
Cited
US4303993A
Cited
US4430584A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-02 | 1989-06-03 | 1989-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-02 | 1993-06-03 | 1993-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-02 | 1997-06-03 | 1997-12-03 | $7700.00 | Window Closed / Lapsed |