Noise removing circuit

Claim 2

A noise removing circuit for removing noise of a duration shorter than a predetermined period of time from an input signal of binary signal configuration, comprising: monitor means for monitoring the input signal to generate an input change signal indicative of whether each time interval occurring between a significant instant detected and a just succeeding significant instant in the input signal is longer or shorter than said predetermined period of time; a one-bit memory for delivery of an output signal; selection means connected to said monitor means and said one-bit memory for selectively applying the input signal or the output signal to said one-bit memory in dependence upon the state of the input change signal, so that noise of the duration shorter than said predetermined period of time is not included in the output signal, said monitor means comprises a first D flip-flop having a D-terminal for receiving said input signal, a second D flip-flop having a D-terminal for receiving the Q output of the first D flip-flop and a Q output connected to one input of said selection means, an exclusive OR circuit having two input terminals for receiving the Q output of the first D flip-flop and the Q output of the second D flip-flop, respectively, and an output for developing said input change signal, said predetermined period of time being less than one clock duration of clock pulses applied to said first D flip-flop and said second D flip-flop.

Claim 3

A noise removing circuit for removing noise of a duration shorter than a predetermined period of time from an input signal of binary signal configuration, comprising: monitor means for monitoring the input signal to generate an input change signal indicative of whether each time interval occurring between a significant instant detected and a just succeeding significant instant in the input signal is longer or shorter than said predetermined period of time; a one-bit memory for delivery of an output signal; selection means connected to said monitor means and said one-bit memory for selectively applying the input signal or the output signal to said one-bit memory in dependence upon the state of the input change signal, so that noise of the duration shorter than said predetermined period of time is not included in the output signal, said monitor means comprises a first D flip-flop having a D-terminal for receiving said input signal, a second D flip-flop having a D-terminal for receiving the Q output of the first D flip-flop and a Q output connected to one input of said selection means, an exclusive OR circuit having two input terminals for receiving the Q output of the first D flip-flop and the Q output of the second D flip-flop, respectively, and an output, and a change decision circuit connected to the output of the exclusive OR circuit to provide an input change signal indicative of whether each time interval is longer or shorter than said predetermined time; which is more than one clock duration of clock pulses applied to said first D flop-flop and said second D flip-flop.

Claim 4

A noise removing circuit for removing noise of a duration shorter than a predetermined period of time from an input signal of binary signal configuration, comprising: monitor means for monitoring the input signal to generate an input change signal indicative of whether each time interval occurring between a significant instant detected and a just succeeding significant instant in the input signal is longer or shorter than said predetermined period of time; a one-bit memory for delivery of an output signal; selection means connected to said monitor means and said one-bit memory for selectively applying the input signal or the output signal to said one-bit memory in dependence upon the state of the input change signal, so that noise of the duration shorter than said predetermined period of time is not included in the output signal, said monitor means comprises a first D flip-flop having a D-terminal for receiving said input signal, a second D flip-flop having a D-terminal for receiving the Q output of the first D flip-flop and a Q output connected to one input of said selection means, an exclusive OR circuit having two input terminals for receiving the Q output of the first D flip-flop and the Q output of the second D flip-flop, respectively, and an output, and a change decision circuit connected to the output of the exclusive OR circuit to provide an input change signal indicative of whether each time interval is longer or shorter than said predetermined time; which is more than one clock duration of clock pulses applied to said first D flop-flop and said second D flip-flop.

Claim 5

A noise removing circuit according to claim 2, in which said change decision circuit comprises a J-K flip-flop having a J-terminal for receiving the output of the exclusive OR circuit, a scale-of-M counter (2 M ≦an integer N less than zero) having an input terminal for receiving the Q output of the J-K flip-flop, an AND circuit having inputs connected to the scale-of-M counter and an output for developing the input change signal, and an OR circuit for clearing the scale-of-M counter in response to the output of the exclusive OR circuit or the output of the AND circuit.

Claim 6

A noise removing circuit according to claim 2, in which said change decision circuit comprises a shift register having an input for receiving the output of the exclusive OR circuit and (N+1) outputs, an OR circuit having N inputs for receiving N outputs of the shift register and an output, and input means for applying the output of the exclusive OR circuit to the input of the shift register in response to no output of said OR circuit, the input change signal being obtained from the (N+1)th output of the shift register.