Pulse width discriminator

Claim 2

In a pulse width discriminator apparatus having an input pulse source, an output signal, which is extended by a predetermined time after termination of the input pulse, and which occurs only after the predetermined time, so that no output pulses occur in the case of input pulses that are shorter than the predetermined time, and so that output pulses the width of which corresponds to the input pulses are sent when the input pulses are longer than the predetermined time, the improvement comprising: A. a timing pulse generator, B. a first counter, C. means to transmit timing pulses to the first counter during occurrence of input pulses, and means responsive to the first counter for commencing an output pulse after a presettable number of timing pulses is counted by the first counter, D. a second counter which can be preset to the same number as the first counter, E. means activated upon termination of input pulses that exceed the predetermined time for starting the second counter to also count timing pulses, and F. means for sending an impulse for causing an end of the output pulse when the second counter reaches the preset number in counting its input timing pulses.

Claim 3

An impulse-width discriminator according to claim 1, further comprising: A. a first AND circuit, having a first input point connected to the input pulse soUrce for receiving the input pulses, having a second input point which is connected to the timing pulse generator, and having an output point of the AND circuit connected to a timing input point of the first counter, B. an OR circuit for passing signals to a discriminator output, C. a first flip-flop, wherein an output point of the first counter which sends a pulse after the presettable numerical value has been reached is connected to one input point of the first flip-flop, wherein an output signal of the first flip-flop passes to the discriminator output point by way of the OR circuit, D. a second flip-flop, wherein the output point of the first flip-flop is also connected to one of the input points of the second flip-flop, an output point of the second flip-flop being connected to a second input point of the OR circuit E. a second AND circuit having one input point connected to the output point of the second flip-flop, and, wherein the second flip-flop is reversed by way of the second counter, and wherein reversal input impulses, inverted by an inverter, are passed to the first counter as well as to the first flip-flop.

Claim 4

An impulse width discriminator according to claim 1, comprising: A. a first start-stop oscillator controlled by the input pulses for transmitting timing pulses to the first counter only durig times in which the input pulses occur, B. a first flip-flop having one input point connected to an output point of the first counter, C. an OR circuit for passing signals, including signals from the output point of the first flip-flop to an output point of the impulse width discriminator, D. a second flip-flop having an input point connected to the output point of the first flip-flop, one output point of the second flip-flop being likewise connected by way of the OR circuit to the output point of the impulse width discriminator, and E. a second start-stop oscillator having a control input point connected to the one output point of the second flip-flop to provide pulses to the second counter, an output point of the second counter being connected to a further input point of the second flip-flop, and a further output point of the second flip-flop being connected to a reversing input point of the second counter by way of a monostable circuit.

Claim 5

Pulse width discriminator apparatus comprising input means for receiving input pulses, timing means connected to the input means for transmitting timing pulses during input pulses, counting means connected to the timing means for producing a signal when a predetermined number of timing pulses has been counted during an inpput pulse, bistable means connected to the counting means for producing a first level in the presence of such a signal from the counting means, reset means connected at its input to the input means and at its output to the counting means and to the bistable means for resetting the counting means and setting the bistable means to a second level upon termination of an input pulse, and output means connected to the bistable means for producing an output during the first level produced by the bistable means.

Claim 6

Pulse width discriminator apparatus comprising input means for receiving input pulses, timing means connected to the input means for transmitting timing pulses during input pulses, counting means connected to the timing means for producing a signal when a predetermined number of timing pulses has been counted during an inpput pulse, bistable means connected to the counting means for producing a first level in the presence of such a signal from the counting means, reset means connected at its input to the input means and at its output to the counting means and to the bistable means for resetting the counting means and setting the bistable means to a second level upon termination of an input pulse, and output means connected to the bistable means for producing an output during the first level produced by the bistable means.

Claim 7

The apparatus of claim 4 wherein the bistable means is a first bistable means, and further comprising a second bistable means connected to an output of the first bistable means for beginning a one level when the first level changes to the second level, second counting means connected to the second bistable means and to the timing means for counting timing pulses while the second bistable means is in the said one level, and the second counting means having further connection to the second bistable means for changing the second bistable means to a second condition to produce another level when a predetermined number of timing pulses is counted by the second counting means, and wherein the output means has gate means connected to the first and second bistable means for producing an Output during the first level and said one level.

Claim 8

The apparatus of claim 5 wherein the timing means comprises a timing pulse generator and first and second AND gates with inputs connected to the generator, wherein the input pulse source is connected to an input of the first AND gate, and wherein an output of the first AND gate is connected to the first counting means, and wherein the second AND gate has an input connected to the second bistable means and an output connected to the second counting means.

Claim 9

The apparatus of claim 5 wherein the timing means comprises first and second oscillating means, the first oscillating means having an input connected to the input pulse source and having an output connected to the first counting means, and the second oscillating means having an input connected to the second bistable means and having an output connected to the second counting means.

Claim 10

Pulse width discriminator apparatus comprising A. a source of input pulses, B. a source of timing pulses, C. a counter connected to the source of timing pulses for counting a predetermined number of timing pulses during an input pulse and for producing a signal when the predetermined number is exceeded, D. a first flip-flop connected to the counter for producing a first stable state during a signal from the counter, E. reset means connected at its input to the source of input pulses and at its output, to the counter and to the first flip-flop for setting the counter and first flip-flop at zero upon termination of an input pulse, and F. an output connected to the first flip-flop.

Claim 11

Pulse width discriminator apparatus comprising A. a source of input pulses, B. a source of timing pulses, C. a counter connected to the source of timing pulses for counting a predetermined number of timing pulses during an input pulse and for producing a signal when the predetermined number is exceeded, D. a first flip-flop connected to the counter for producing a first stable state during a signal from the counter, E. reset means connected at its input to the source of input pulses and at its output, to the counter and to the first flip-flop for setting the counter and first flip-flop at zero upon termination of an input pulse, and F. an output connected to the first flip-flop.

Claim 12

The apparatus of claim 8, further comprising a second flip-flop connected to the first flip-flop for producing a first stable state beginning at a transition from first to second state by the first flip-flop, a second counter connected to the timing pulse source and to the second flip-flop for counting a predetermined number of timing pulses when the second flip-flop is in a first state, the second counter having a further connection to the second flip-flop for changing the second flip-flip to a second stable state after counting a predetermined number of timing pulses, and an OR gate connected to the first and second flip-flops for combining first stable state outputs of the flip-flops.

Claim 13

The apparatus of claim 5 further comprising reset means connected between the second bistable means and the second counting means for resetting the second counting means to the second condition.