Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers

Claim 2

A computer system in which virtual addresses, used by programs executed by the computer system, are translated to physical addresses in order to access physical memory locations in memory storage devices within the computer system, said system comprising: a processor comprising a primary translation look-aside buffer containing a first set of data representative of a first set of recently used virtual-to-physical address translations and TLB fetch hardware coupled to the primary translation look-aside buffer; and a physical memory coupled to the processor by a first bus, said physical memory comprising a secondary translation look-aside buffer coupled to the first bus for providing a second set of data to the processor, said second set of data representative of a second set of virtual-to-physical address translations, and a virtual address translation table means coupled to the secondary translation look-aside buffer for providing a third set of data to the processor, said third set of data representative of all virtual-to-physical address translations needed to access data located in the physical memory; wherein when the processor searches for a virtual-to-physical address translation in order to use the virtual-to-physical address translation to access a physical memory location, the processor will obtain the virtual-to-physical address translation from the primary look-aside buffer when the virtual-to-physical address translation is in the primary look-aside buffer, and when the virtual-to-physical address translation is not in the primary look-aside buffer, the TLB fetch hardware will fetch data from the secondary translation look-aside buffer when the virtual-to-physical address is in the secondary translation look-aside buffer, and when the virtual-to-physical address translation is not in the secondary translation look-aside buffer, the TLB fetch hardware will generate a trap after which the processor will search the virtual address translation table using software.

Claim 3

A computer system as in claim 1, wherein the virtual address translation table means comprises hashing means for distributing virtual address entries throughout allocated portions of the physical memory.

Claim 4

A computer system as in claim 3, wherein the hashing means comprises a hashing function located in software.

Claim 5

A computer system as in claim 1, wherein the memory access speed of the primary translation look-aside buffer is greater than the memory access speed of the secondary translation look-aside buffer.

Claim 6

A computer system as in claim 4, wherein the memory size of the primary translation look-aside buffer is less than the memory size of the secondary translation look-aside buffer.

Claim 7

A computer system as in claim 1, wherein the third set of data comprises a set of virtual addresses corresponding to a set of physical addresses located in the physical memory.

Claim 8

A computer system in which virtual addresses, used by programs executed by the computer system, are translated to physical addresses in order to access physical memory locations in memory storage devices within the computer system, said system comprising: a processor comprising a primary translation look-aside buffer containing a first set of data representative of a first set of recently used virtual-to-physical address translations and TLB fetch hardware coupled to the primary translation look-aside buffer; a secondary translation look-aside buffer coupled to the primary translation look-aside buffer by a TLB bus for providing a second set of data to the processor, said second set of data representative of a second set of virtual-to-physical address translations; and a physical memory coupled to the processor by a first bus, said physical memory comprising a virtual address translation table means coupled to the secondary translation look-aside buffer for providing a third set of data to the processor, said third set of data representative of all virtual-to-physical address translations needed to access data located in the physical memory; wherein when the processor searches for a virtual-to-physical address translation in order to use the virtual-to-physical address translation to access a physical memory location, the processor will obtain the virtual-to-physical address translation from the primary look-aside buffer when the virtual-to-physical address translation is in the primary look-aside buffer, and when the virtual-to-physical address translation is not in the primary look-aside buffer, the TLB fetch hardware will fetch data from the secondary translation look-aside buffer when the virtual-to-physical address is in the secondary translation look-aside buffer, and when the virtual-to-physical address translation is not in the secondary translation look-aside buffer, the TLB fetch hardware will generate a trap after which the processor will search the virtual address translation table using software.

Claim 9

A computer system in which virtual addresses, used by programs executed by the computer system, are translated to physical addresses in order to access physical memory locations in memory storage devices within the computer system, said system comprising: a processor comprising a primary translation look-aside buffer containing a first set of data representative of a first set of recently used virtual-to-physical address translations and TLB fetch hardware coupled to the primary translation look-aside buffer; a secondary translation look-aside buffer coupled to the primary translation look-aside buffer by a TLB bus for providing a second set of data to the processor, said second set of data representative of a second set of virtual-to-physical address translations; and a physical memory coupled to the processor by a first bus, said physical memory comprising a virtual address translation table means coupled to the secondary translation look-aside buffer for providing a third set of data to the processor, said third set of data representative of all virtual-to-physical address translations needed to access data located in the physical memory; wherein when the processor searches for a virtual-to-physical address translation in order to use the virtual-to-physical address translation to access a physical memory location, the processor will obtain the virtual-to-physical address translation from the primary look-aside buffer when the virtual-to-physical address translation is in the primary look-aside buffer, and when the virtual-to-physical address translation is not in the primary look-aside buffer, the TLB fetch hardware will fetch data from the secondary translation look-aside buffer when the virtual-to-physical address is in the secondary translation look-aside buffer, and when the virtual-to-physical address translation is not in the secondary translation look-aside buffer, the TLB fetch hardware will generate a trap after which the processor will search the virtual address translation table using software.

Claim 10

A computer system as in claim 7, wherein the virtual address translation table means comprises hashing means for distributing virtual address entries throughout allocated portions of the physical memory.

Claim 11

A computer system as in claim 8, wherein the hashing means comprises a hashing function located in software.

Claim 12

A computer system as in claim 7, wherein the memory access speed of the priary translation look-aside buffer is greater than the memory access speed of the secondary translation look-aside buffer.

Claim 13

A computer system as in claim 10, wherein the memory size of the primary translation look-aside buffer is less than the memory size of the secondary translation look-aside buffer.

Claim 14

A computer system as in claim 7, wherein the third set of data comprises a set of virtual addresses corresponding to a set of physical addresses located in the physical memory.

Claim 17

A method as in claim 13 further comprising during step (c) the step of (d) interrupting operation of the processor.

Claim 20

A method as in claim 15 further comprising during step (c) the step of (d) interrupting operation of the processor.