Memory address control apparatus with separate translation look aside buffers for a data processor using a virtual memory technique

Claim 2

In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation coupled to said operand fetch unit for translating only logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein each of said translating means comprises, a logical address register (91) responsive to a logical address from its respective fetch unit for holding said logical address, the latter comprising a page or segment name plus a displacement, a translation look aside buffer (TLB) memory array (93) responsive to the output from an address decoder means and having T sets, each set having m T compartments, each compartment storing a part of a logical address and the corresponding real address in the MMU, address decoder means (92) responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having m T compartments in said TLB, comparison means (94-1 . . . 94-m T ) responsive to the logical addresses in said register and said TLB for comparing the logical addresses in said register with those in said TLB, and output means (95-1 . . . 95-m T , 96) responsive to said comparison means for outputting one real address out of the addresses in the selected read from said TLB.

Claim 3

In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating only logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein each of said translating means comprises, a logical address register (91) responsive to a logical address from its respective fetch unit for holding said logical address, the latter comprising a page or segment name plus a displacement, a translation look aside buffer (TLB) memory array (93) responsive to th output from an address decoder means and having T sets, each set having m T compartments, each compartment storing a part of a logical address and the corresponding real address in the MMU, address decoder means (92) responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having m T compartments in said TLB, comparison means (94-1 . . . 94-m T ) responsive to the logical addresses read out from said register and said TLB for comparing the logical addresses in said set having been read-out with a portion of said logical address in said register, output means (95-1 . . . 95-m T , 96) responsive to said comparison means for outputting one real address out of the addresses in the selected set read from said TLB, and means for accessing responsive to a portion of the logical address in said logical address register and the real address from said output means, said means for accessing comprising addressing means (201) for holding an address representative of the address of an instruction and data in said MMU respectively, cache-memory means, means (203) responsive to a portion of said address for reading out a set of cache-memory means stored addresses from said cache-memory means, means (205-1 . . . 205-n) for comparing each of said read-out cache-memory means stored addresses with another part of said address in said addressing means to detect which, if any, of said cache-memory means stored addresses corresponds to said address in said addressing means, means (206) responsive to a portion of said address in said addressing means for reading out a set of cache-memory means stored instructions and data, respectively, and means (209-1 . . . 209-n, 210) responsive to said cache stored address comparison means for selecting for further processing the instruction and data from said read-out set of instructions and data in cache memory means storage locations corresponding to the read-out cache address which corresponds to a portion of said address in said addressing means.

Claim 4

In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating only logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein each of said translating means comprises, a logical address register (91) responsive to a logical address from its respective fetch unit for holding said logical address, the latter comprising a page or segment name plus a displacement, a translation look aside buffer (TLB) memory array (93) responsive to th output from an address decoder means and having T sets, each set having m T compartments, each compartment storing a part of a logical address and the corresponding real address in the MMU, address decoder means (92) responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having m T compartments in said TLB, comparison means (94-1 . . . 94-m T ) responsive to the logical addresses read out from said register and said TLB for comparing the logical addresses in said set having been read-out with a portion of said logical address in said register, output means (95-1 . . . 95-m T , 96) responsive to said comparison means for outputting one real address out of the addresses in the selected set read from said TLB, and means for accessing responsive to a portion of the logical address in said logical address register and the real address from said output means, said means for accessing comprising addressing means (201) for holding an address representative of the address of an instruction and data in said MMU respectively, cache-memory means, means (203) responsive to a portion of said address for reading out a set of cache-memory means stored addresses from said cache-memory means, means (205-1 . . . 205-n) for comparing each of said read-out cache-memory means stored addresses with another part of said address in said addressing means to detect which, if any, of said cache-memory means stored addresses corresponds to said address in said addressing means, means (206) responsive to a portion of said address in said addressing means for reading out a set of cache-memory means stored instructions and data, respectively, and means (209-1 . . . 209-n, 210) responsive to said cache stored address comparison means for selecting for further processing the instruction and data from said read-out set of instructions and data in cache memory means storage locations corresponding to the read-out cache address which corresponds to a portion of said address in said addressing means.

Claim 5

In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating only logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein each of said translating means comprises, a logical address register (91) responsive to a logical address from its respective fetch unit for holding said logical address, the latter comprising a page or segment name plus a displacement, a translation look aside buffer (TLB) memory array (93) responsive to the output from an address decoder means and having T sets, each set having m T compartments, each compartment storing a part of a logical address and the corresponding real address in the MMU, address decoder means (92) responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having m T compartments in said TLB, comparison means (94-1 . . . 94-m T ) responsive to the logical addresses read out from said register and said TLB for comparing the logical addresses in said set having been read-out with a portion of said logical address in said register, output means (95-1 . . . 95-m T , 96) responsive to said comparison means for outputting one real address out of the addresses in the selected set read from said TLB, and means for accessing responsive to a portion of the logical address in said logical address register and the real address from said input means, said means for accessing comprising addressing means (201) for holding an address representative of the address of an instruction and data in said MMU respectively, cache-memory means, means (203) responsive to a portion of said address for reading out a set of cache-memory means stored addresses from said cache-memory means, means (205-1 . . . 205-n) for comparing each of said read-out cache-memory means stored addresses with another part of said address in said addressing means to detect which, if any, of said cache-memory means stored addresses corresponds to said address in said addressing means, means responsive to a portion of said address in said addressing means and an address corresponding to the comparison result from said cache stored address comparison means for reading out cache-memory means stored instructions and data, respectively.

Claim 6

In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating only logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein each of said translating means comprises, a logical address register (91) responsive to a logical address from its respective fetch unit for holding said logical address, the latter comprising a page or segment name plus a displacement, a translation look aside buffer (TLB) memory array (93) responsive to the output from an address decoder means and having T sets, each set having m T compartments, each compartment storing a part of a logical address and the corresponding real address in the MMU, address decoder means (92) responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having m T compartments in said TLB, comparison means (94-1 . . . 94-m T ) responsive to the logical addresses read out from said register and said TLB for comparing the logical addresses in said set having been read-out with a portion of said logical address in said register, output means (95-1 . . . 95-m T , 96) responsive to said comparison means for outputting one real address out of the addresses in the selected set read from said TLB, and means for accessing responsive to a portion of the logical address in said logical address register and the real address from said input means, said means for accessing comprising addressing means (201) for holding an address representative of the address of an instruction and data in said MMU respectively, cache-memory means, means (203) responsive to a portion of said address for reading out a set of cache-memory means stored addresses from said cache-memory means, means (205-1 . . . 205-n) for comparing each of said read-out cache-memory means stored addresses with another part of said address in said addressing means to detect which, if any, of said cache-memory means stored addresses corresponds to said address in said addressing means, means responsive to a portion of said address in said addressing means and an address corresponding to the comparison result from said cache stored address comparison means for reading out cache-memory means stored instructions and data, respectively.

Claim 7

In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating only logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein each of said translating means comprises, a logical address register (91) responsive to a logical address from its respective fetch unit for holding said logical address, the latter comprising a page or segment name plus a displacement, a translation look aside buffer (TLB) memory array (93) responsive to the output from an address decoder means and having T sets, each set having m T compartments, each compartment storing a part of a logical address and the corresponding real address in the MMU, address decoder means (92) responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having m T compartments in said TLB, comparison means (94-1 . . . 94-m T ) responsive to the logical addresses read out from said register and said TLB for comparing the logical addresses in said set having been read-out with a portion of said logical address in said register and for selecting the read-out logical address corresponding to the portion of said logical address in said register, output means (95-1 . . . 95-m T , 96) responsive to said comparison means for outputting one real address out of the addresses in the selected set read from said TLB, and cache-memory means, means (203) responsive to a portion of said logical address for reading out a set of cache-memory means stored addresses from said cache-memory means, and means (205-1, . . . , 205-n) for comparing each of said read-out cache-memory means stored addresses with said output means to detect which, if any, of said cache-memory means stored addresses corresponds to said address from said output means.

Claim 8

In a data processing system memory address control apparatus connected to a main memory unit (MMU) and a processing unit (PU) including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in the MMU into corresponding real addresses of the MMU; and operand data address translation means coupled to said operand fetch unit for translating only logical addresses for reading out data words stored in the MMU into corresponding real addresses of the MMU; wherein each of said translating means comprises, a logical address register (91) responsive to a logical address from its respective fetch unit for holding said logical address, the latter comprising a page or segment name plus a displacement, a translation look aside buffer (TLB) memory array (93) responsive to the output from an address decoder means and having T sets, each set having m T compartments, each compartment storing a part of a logical address and the corresponding real address in the MMU, address decoder means (92) responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having m T compartments in said TLB, comparison means (94-1 . . . 94-m T ) responsive to the logical addresses read out from said register and said TLB for comparing the logical addresses in said set having been read-out with a portion of said logical address in said register and for selecting the read-out logical address corresponding to the portion of said logical address in said register, output means (95-1 . . . 95-m T , 96) responsive to said comparison means for outputting one real address out of the addresses in the selected set read from said TLB, and cache-memory means, means (203) responsive to a portion of said logical address for reading out a set of cache-memory means stored addresses from said cache-memory means, and means (205-1, . . . , 205-n) for comparing each of said read-out cache-memory means stored addresses with said output means to detect which, if any, of said cache-memory means stored addresses corresponds to said address from said output means.