Electrical waveform generator means and methods

Claim 2

An electrical waveform generator, comprising: memory means for storing a plurality of data points representing sequential amplitude values of a desired waveform; digital-to-analog converter means for converting said data points to analog voltage for generating said desired waveform; and means for selectively coupling said data points to said converter means, including means for selecting groups of said data points and for selectively performing nested looping through said groups for producing a waveform.

Claim 3

The generator of claim 1, wherein said means for selecting and for selectively looping includes means for selecting the number of data points in each group, the number of groups of data points and the number of loops performed for each group.

Claim 4

In an electrical waveform generator of the type having memory means for storing a plurality of data points representing sequential amplitude values of a desired waveform, digital-to-analog converter means for converting said data points to analog voltage for generating said desired waveform, and means for selectively coupling said data points to said converter means for producing a waveform, wherein the improvement compises said means for selectively coupling including: first and second parallel memory means for storing operation data and operation codes, respectively; program counter means for clocking said first and second memory means in response to said operation data; loop counter means for enabling said looping of said data point groups in response to said operation data; memory address counter means for controlling the data points coupled to said converter means in response to said operation data; and instruction decoder means coupled to the second parallel memory means for generating control signals coupled to said program counter means, said loop counter means and said memory address counter means in response to said operation codes, said program counter means, said loop counter means and said memory address counter means being coupled to receive operation data from the first parallel memory means.

Claim 5

In an electrical waveform generator of the type having memory means for storing a plurality of data points representing sequential amplitude values of a desired waveform, digital-to-analog converter means for converting said data points to analog voltage for generating said desired waveform, and means for selectively coupling said data points to said converter means for producing a waveform, wherein the improvement compises said means for selectively coupling including: first and second parallel memory means for storing operation data and operation codes, respectively; program counter means for clocking said first and second memory means in response to said operation data; loop counter means for enabling said looping of said data point groups in response to said operation data; memory address counter means for controlling the data points coupled to said converter means in response to said operation data; and instruction decoder means coupled to the second parallel memory means for generating control signals coupled to said program counter means, said loop counter means and said memory address counter means in response to said operation codes, said program counter means, said loop counter means and said memory address counter means being coupled to receive operation data from the first parallel memory means.

Claim 6

The improvement of claim 3, wherein said control signals generated by said instruction decoder include clocking and preset signals for each said respective counter means.

Claim 7

The improvement of claim 3, wherein said loop counter means includes a plurality of loop counters.

Claim 10

The method of claim 6, wherein said step of selectively looping includes selecting the number of groups of data points for looping and selecting the number of loops performed for each group.

Claim 11

The method of claim 6, wherein said selectively coupling includes: storing operation codes and operation data in first and second parallel memory means; sequentially addressing said first and second memory means with a program counter means responsive to said operation data; controlling the number of loops performed of each of said groups of data points with a loop counter means responsive to said operation data; controlling the data points coupled with a memory address counter means responsive to said operation data; coupling said operation data to the program counter means, the loop counter means and the memory address counter means; and controlling said program counter means, said loop counter means and said memory address counter means in response to said operation data with an instruction decoder means coupled to receive said operation codes.

Claim 12

The method of claim 8, wherein said controlling each of said counter means includes generating respective clock and preset control signals for each said counter means.