Patent US6230218B1 successfully refreshed from Google Patents.
US4769628A
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High speed analog-to-digital converter utilizing multiple, identical stages
Assignee: Individual
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Filing: 1987-06-11
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Granted: 1988-09-06
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Expires: 2007-06-11
Abstract
Abstract An analog-to-digital converter circuit includes a series of substantially identical stages, each receiving an incoming analog voltage. Reference terminals of the initial stage are biased to an initial reference voltage and ground, with subsequent first and second reference voltages determined in each preceding stage. A voltage divider consisting of a pair of matched resistors provides an output of one-half the reference voltage to a comparator. The comparator, having as its other input the incoming analog signal, generates a binary "one" or "zero" depending on whether the incoming signal is greater or less than the voltage divider output. The binary signal also controls switching circuitry which provides first and second reference signals to the next stage of the A/D converter. Responsive to a binary one from the converter, these reference signals are the reference voltage and one-half the reference voltage, respectively. A binary zero produces one-half the reference voltage and ground as the respective first and second reference signals.
Inventors
- 👤 David S. Hellerman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:59
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/42
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
353 words
A multiple stage analog-to-digital converter, including: an analog input terminal for receiving an analog voltage, a first reference terminal biased to a first predetermined voltage greater than the analog voltage, and a second reference terminal biased to a second predetermined voltage less than the analog voltage; and a plurality of stages of circuitry connected to said terminals for generating a binary word of n bits corresponding to said analog voltage, wherein n is an integer; each of said stages including a voltage dividing means for receiving first and second reference voltage signals and generating a divider output voltage halfway between the voltage levels of said first and second reference voltage signals; a comparator means, having as inputs said analog voltage and a comparator reference input voltage substantially equal to said divider output voltage, for generating a first binary signal whenever said analog voltage is greater than said comparator reference input voltage, and a second binary signal whenever said analog voltage is less than said comparator reference input voltage; a buffering element for receiving said divider output voltage and generating a buffering output voltage dependent upon said divider output voltage; and a switching means receiving as voltage inputs said first reference voltage, second reference voltage and buffering output voltage, and further receiving said binary signal as a control input, said switching means being configured to break before make and generating said first reference voltage and buffering output voltage as first and second switching output voltages, respectively, responsive to receiving said first binary signal as said control input, and generating said buffering output voltage and said second reference voltage as said first and second switching output voltages, respectively, responsive to receiving said second binary signal as said control input; wherein said first and second predetermined voltages comprise the first and second reference voltages to the first one of said stages, and the first and second switching output voltages of each stage comprise substantially the first and second reference voltages provided to the next subsequent one of said stages, and said comparators cooperate to generate a binary word of n bits corresponding to said analog voltage.
Claim 2
Dependent Claim
353 words
A multiple stage analog-to-digital converter, including: an analog input terminal for receiving an analog voltage, a first reference terminal biased to a first predetermined voltage greater than the analog voltage, and a second reference terminal biased to a second predetermined voltage less than the analog voltage; and a plurality of stages of circuitry connected to said terminals for generating a binary word of n bits corresponding to said analog voltage, wherein n is an integer; each of said stages including a voltage dividing means for receiving first and second reference voltage signals and generating a divider output voltage halfway between the voltage levels of said first and second reference voltage signals; a comparator means, having as inputs said analog voltage and a comparator reference input voltage substantially equal to said divider output voltage, for generating a first binary signal whenever said analog voltage is greater than said comparator reference input voltage, and a second binary signal whenever said analog voltage is less than said comparator reference input voltage; a buffering element for receiving said divider output voltage and generating a buffering output voltage dependent upon said divider output voltage; and a switching means receiving as voltage inputs said first reference voltage, second reference voltage and buffering output voltage, and further receiving said binary signal as a control input, said switching means being configured to break before make and generating said first reference voltage and buffering output voltage as first and second switching output voltages, respectively, responsive to receiving said first binary signal as said control input, and generating said buffering output voltage and said second reference voltage as said first and second switching output voltages, respectively, responsive to receiving said second binary signal as said control input; wherein said first and second predetermined voltages comprise the first and second reference voltages to the first one of said stages, and the first and second switching output voltages of each stage comprise substantially the first and second reference voltages provided to the next subsequent one of said stages, and said comparators cooperate to generate a binary word of n bits corresponding to said analog voltage.
Claim 3
Dependent Claim
41 words
The analog-to-digital converter of claim 1 wherein: each of said dividing means includes first and second dividing resistors of substantially equal resistance connected in series, with the output of each dividing means positioned between its associated first and second dividing resistors.
Claim 4
Dependent Claim
26 words
The analog-to-digital converter of claim 1 further including: a binary register means for receiving and holding the binary signals of said comparator means of said stages.
Claim 5
Dependent Claim
41 words
The analog-to-digital converter of claim 2 wherein: said buffering element comprises a unity gain following means receiving the output of its associated one of said dividing means and provides said buffering output voltage to its associated one of said switching means.
Claim 6
Dependent Claim
18 words
The analog-to-digital converter of claim 4 wherein: each of said unity gain following means comprises an operational amplifier.
Claim 7
Dependent Claim
13 words
The analog-to-digital converter of claim 5 wherein: said second predetermined voltage is ground.
Claim 8
Dependent Claim
24 words
The analog-to-digital converter of claim 2 wherein: the resistance of all of said first dividing resistors and second dividing resistors is substantially the same.
Claim 9
Dependent Claim
56 words
The analog-to-digital converter of claim 1 wherein: each of said switching means includes a bank of four CMOS switches including first and second CMOS switches closed responsive to receiving said first binary signal from their associated comparator means, and third and fourth CMOS switches closed responsive to receiving said second digital output from said comparator means.
Claim 10
Dependent Claim
303 words
A multiple stage analog-to-digital converter, including: an analog input terminal for receiving an analog voltage, a first reference terminal biased to a first predetermined voltage greater than the analog voltage, and a second reference terminal biased to a second predetermined voltage less than the analog voltage; and a plurality of stages of circuitry connected to said terminals for generating a binary word of n bits corresponding to said analog voltage, wherein n is an integer; each of said stages including a voltage dividing means for receiving first and second reference voltage signals and generating a divider output voltage halfway between the voltage levels of said first and second reference voltage signals; a comparator means, having as inputs said analog voltage and said divider output voltage, for generating a first binary signal whenever said analog voltage is greater than said divider output voltage, and a second binary signal whenever said analog voltage is less than said divider output voltage; and a switching means receiving as voltage inputs said first reference voltage, second reference voltage and divider output voltage, and further receiving said binary signal as a control input, said switching means generating said first reference voltage and divider output voltage as first and second switching output voltages, respectively, responsive to receiving said first binary signal as said control input, and generating said divider output voltage and said second reference voltage as said first and second switching output voltages, respectively, responsive to receiving said second binary signal as said control input; and a first buffering element comprising a unity gain follower means between the first switching output of each of said switching means and the next subsequent one of said stages, and a second buffering element comprising a unity gain follower means between the second switching output of said switching means and said subsequent stage.
Claim 11
Dependent Claim
303 words
A multiple stage analog-to-digital converter, including: an analog input terminal for receiving an analog voltage, a first reference terminal biased to a first predetermined voltage greater than the analog voltage, and a second reference terminal biased to a second predetermined voltage less than the analog voltage; and a plurality of stages of circuitry connected to said terminals for generating a binary word of n bits corresponding to said analog voltage, wherein n is an integer; each of said stages including a voltage dividing means for receiving first and second reference voltage signals and generating a divider output voltage halfway between the voltage levels of said first and second reference voltage signals; a comparator means, having as inputs said analog voltage and said divider output voltage, for generating a first binary signal whenever said analog voltage is greater than said divider output voltage, and a second binary signal whenever said analog voltage is less than said divider output voltage; and a switching means receiving as voltage inputs said first reference voltage, second reference voltage and divider output voltage, and further receiving said binary signal as a control input, said switching means generating said first reference voltage and divider output voltage as first and second switching output voltages, respectively, responsive to receiving said first binary signal as said control input, and generating said divider output voltage and said second reference voltage as said first and second switching output voltages, respectively, responsive to receiving said second binary signal as said control input; and a first buffering element comprising a unity gain follower means between the first switching output of each of said switching means and the next subsequent one of said stages, and a second buffering element comprising a unity gain follower means between the second switching output of said switching means and said subsequent stage.
Claim 12
Dependent Claim
20 words
The analog-to-digital converter of claim 9 further including: a bypass capacitor between said first and second unity gain follower means.
Claim 13
Dependent Claim
18 words
The analog-to-digital converter of claim 9 wherein: said first and second unity gain follower means comprise operational amplifiers.
Claim 14
Dependent Claim
38 words
The analog-to-digital converter of claim 11 further including: first, second and third substantially equal auxiliary resistances connected in series between each of said switching means and said first reference voltage, second reference voltage and divider output voltage, respectively.
Claim 15
Dependent Claim
52 words
The analog-to-digital converter of claim 9 wherein: each of said dividing means includes first and second dividing resistors connected in series, with the output of each dividing means positioned between its associated first and second dividing resistors, and wherein all of said first and second dividing resistors have substantially the same resistance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1991-09-06 | 1992-03-07 | 1992-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-06 | 1996-03-07 | 1996-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-06 | 2000-03-07 | 2000-09-06 | $7700.00 | Window Closed / Lapsed |