US3918050A
Expired / Lapsed
US
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Analog-to-digital conversion apparatus
Assignee: Boeing North American Inc
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Filing: 1974-11-18
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Granted: 1975-11-04
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Expires: 1994-11-18
Abstract
Abstract An analog-to-digital conversion apparatus wherein, in one embodiment, an input analog current is applied to an input of an integrating circuit, while a switching circuit allows a precision reference current to be summed with the input analog current at the input of the integrating circuit during a first mode of operation of the switching circuit and prevents the precision reference current from being applied to the input of the integrating circuit during a second mode of operation of the switching circuit. The integrating circuit generates a first signal proportional to the integral of the sum of any currents applied to its input. In response to the first signal and to clock pulses, generator means develops an incremental pulse width modulated signal to precisely control the first and second modes of operation of the switching circuit. The incremental pulse width modulated signal and clock pulses are then utilized by an output circuit to generate a digital representaion of the amplitude of the input analog current.
Inventors
- 👤 Adrian K Dorsman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:36
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/56; H03M1/52
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
149 words
An analog-to-digital conversion system comprising: first means for generating precision and bias currents; switching means for passing the precision current as an output precision current during a first mode of operation and for directly returning the precision current to said first means during a second mode of operation; integrator means for generating a first signal proportional to the integral of the sum of the bias and output precision currents and an unknown input analog current; second means for generating a second signal in response to the first signal, the second signal having one of first and second states as a function of the amplitude of the first signal; third means responsive to the second signal and to clock pulses for controlling the first and second modes of operation of said switching means and for generating an output pulse rate of clock pulses proportional to the unknown input analog current.
Claim 2
Dependent Claim
149 words
An analog-to-digital conversion system comprising: first means for generating precision and bias currents; switching means for passing the precision current as an output precision current during a first mode of operation and for directly returning the precision current to said first means during a second mode of operation; integrator means for generating a first signal proportional to the integral of the sum of the bias and output precision currents and an unknown input analog current; second means for generating a second signal in response to the first signal, the second signal having one of first and second states as a function of the amplitude of the first signal; third means responsive to the second signal and to clock pulses for controlling the first and second modes of operation of said switching means and for generating an output pulse rate of clock pulses proportional to the unknown input analog current.
Claim 3
Dependent Claim
152 words
An analog-to-digital conversion system comprising: first means for generating a precision current; switching means for passing the precision current as an output precision current during a first mode of operation and for preventing the precision current from being passed as an output precision current during a second mode of operation; integrator means responsive to the output precision current and to an unknown input analog current for generating a first signal proportional to the integral of the sum of the currents applied thereto; second means for generating a first pulse width modulated signal as a function of the first signal; and third means responsive to the first pulse width modulated signal and to clock pulses for generating a second pulse width modulated signal for controlling the first and second modes of operation of said switching means, and for generating an output pulse rate of clock pulses proportional to the unknown input analog current.
Claim 4
Dependent Claim
152 words
An analog-to-digital conversion system comprising: first means for generating a precision current; switching means for passing the precision current as an output precision current during a first mode of operation and for preventing the precision current from being passed as an output precision current during a second mode of operation; integrator means responsive to the output precision current and to an unknown input analog current for generating a first signal proportional to the integral of the sum of the currents applied thereto; second means for generating a first pulse width modulated signal as a function of the first signal; and third means responsive to the first pulse width modulated signal and to clock pulses for generating a second pulse width modulated signal for controlling the first and second modes of operation of said switching means, and for generating an output pulse rate of clock pulses proportional to the unknown input analog current.
Claim 5
Dependent Claim
80 words
The system of claim 2 wherein said second means includes: generator means for developing a second signal; and a comparator coupled to said generator means for generating the first pulse width modulated signal, the first pulse width modulated signal being in a binary one state when the first signal has a first polarity with respect to the second signal and being in a binary zero state when the first signal has a second polarity with respect to the second signal.
Claim 6
Dependent Claim
157 words
An analog to digital conversion apparatus comprising: first means for generating a precision reference current; an integrating circuit having an input, said input adapted to receive an input analog current; switching means for allowing the reference current to be summed with the input analog current at said input during a first mode of operation of said switching means and for preventing the reference current from being applied to said input during a second mode of operation of said switching means, said integrating circuit generating a first signal proportional to the integral of the sum of the currents applied to said input thereof; generator means responsiVe to the first signal for developing a pulse width modulated signal to control the first and second modes of operation of said switching means; and output means responsive to the pulse width modulated signal and to the clock pulses for generating a digital representation of the amplitude of the input analog current.
Claim 7
Dependent Claim
157 words
An analog to digital conversion apparatus comprising: first means for generating a precision reference current; an integrating circuit having an input, said input adapted to receive an input analog current; switching means for allowing the reference current to be summed with the input analog current at said input during a first mode of operation of said switching means and for preventing the reference current from being applied to said input during a second mode of operation of said switching means, said integrating circuit generating a first signal proportional to the integral of the sum of the currents applied to said input thereof; generator means responsiVe to the first signal for developing a pulse width modulated signal to control the first and second modes of operation of said switching means; and output means responsive to the pulse width modulated signal and to the clock pulses for generating a digital representation of the amplitude of the input analog current.
Claim 8
Dependent Claim
55 words
The apparatus of claim 4 wherein said generator means includes: a signal source for developing the clock pulses and a reference signal; and second means responsive to the first signal, reference signal and clock pulses for developing the pulse width modulated signal to control the first and second modes of operation of said switching means.
Claim 9
Dependent Claim
35 words
The apparatus of claim 4 wherein said first means includes: a voltage source for developing a precision reference voltage; and a current source responsive to the precision reference voltage for generating the precision reference current.
Claim 10
Dependent Claim
57 words
The apparatus of claim 6 wherein said first means further includes: bias means, coupled between said voltage source and said input, for applying a bias current to said input, said integrating circuit generating the first signal proportional to the integral of the sum of the reference, bias and input analog currents during the first mode of operation.
Claim 11
Dependent Claim
56 words
The apparatus of claim 4 wherein said switching means includes: a first switch enabled by said generator means to pass the reference current to said input during the first mode of operation; and a second switch enabled by said generator means to return the reference current to said first means during the second mode of operation.
Claim 12
Dependent Claim
18 words
The apparatus of claim 8 wherein each of said first and second switches is a field effect transistor.
Claim 13
Dependent Claim
36 words
The apparatus of claim 5 wherein said signal source includes: a clock generator for generating basic timing pulses; and frequency divider means responsive to the basic timing pulses for developing the clock pulses and reference signal.
Claim 14
Dependent Claim
110 words
The apparatus of claim 5 wherein said second means includes: a generator responsive to the reference signal for developing a preselected signal waveform; a comparator for developing a rectangular waveform in response to the first signal and the preselected signal waveform, the rectangular waveform being in a first binary state when the first signal is in a first polarity relationship with respect to the preselected signal waveform and in a second binary state when the first signal is in a second polarity relationship with respect to the preselected signal waveform; and flip flop means responsive to the rectangular waveform and the clock pulses for developing the pulse width modulated signal.
Claim 15
Dependent Claim
15 words
The apparatus of claim 11 wherein said flip flop means includes a first flip flop.
Claim 16
Dependent Claim
72 words
The apparatus of claim 11 wherein said output means includes: gating means responsive to the pulse width modulated signal for passing clock pulses during the first mode of operation and for blocking clock pulses during the second mode of operation; and counting means responsive to the clock pulses passed by said gate circuit during each first mode of operation for generating a digital representation of the amplitude of the input analog current.
Claim 17
Dependent Claim
31 words
The apparatus of claim 13 wherein said output means further includes an inverter for also applying to said counting means the complements of the clock pulses passed by said gating means.
Claim 18
Dependent Claim
49 words
The apparatus of claim 11 wherein said flip flop means includes: a first delay circuit responsive to the clock pulses for developing first delayed clock pulses; and a first flip flop responsive to the rectangular waveform and the first delayed clock pulses for developing the pulse width modulated signal.
Claim 19
Dependent Claim
75 words
The apparatus of claim 15 wherein said output means includes: a second delay circuit responsive to first delayed clock pulses for developing second delayed clock pulses; a second flip flop responsive to clock pulses, second delaYed clock pulses and the pulse width modulated signal for developing output pulses during the first mode of operation; and counting means responsive to the output pulses for generating a digital representation of the amplitude of the input analog current.
Claim 20
Dependent Claim
56 words
The apparatus of claim 5 wherein said switching means includes: a first switch enabled by said second means to pass the reference current to said input during the first mode of operation; and a second switch enabled by said second means to return the reference current to said first means during the second mode of operation.
Claim 21
Dependent Claim
110 words
The apparatus of claim 17 wherein said second means includes: a generator responsive to the reference signal for developing a preselected signal waveform; a comparator for developing a rectangular waveform in response to the first signal and the preselected signal waveform, the rectangular waveform being in a first binary state when the first signal is in a first polarity relationship with respect to the preselected signal waveform and in a second binary state when the first signal is in a second polarity relationship with respect to the preselected signal waveform; and flip flop means responsive to the rectangular waveform and the clock pulses for developing the pulse width modulated signal.
Claim 22
Dependent Claim
36 words
The apparatus of claim 18 wherein said signal source includes: a clock generator for generating basic timing pulses; and frequency divider means responsive to the basic timing pulses for developing the clock pulses and reference signal.
Claim 23
Dependent Claim
35 words
The apparatus of claim 19 wherein said first means includes: a voltage source for developing a precision reference voltage; and a current source responsive to the precision reference voltage for generating the precision reference current.
Claim 24
Dependent Claim
57 words
The apparatus of claim 20 wherein said first means further includes: bias means, coupled between said voltage source and said input, for applying a bias current to said input, said integrating circuit generating the first signal proportional to the integral of the sum of the reference, bias and input analog currents during the first mode of operation.
Claim 25
Dependent Claim
72 words
The apparatus of claim 21 wherein said output means includes: gating means responsive to the pulse width modulated signal for passing clock pulses during the first mode of operation and for blocking clock pulses during the second mode of operation; and counting means responsive to the clock pulses passed by said gate circuit during each first mode of operation for generating a digital representation of the amplitude of the input analog current.
Claim 26
Dependent Claim
49 words
The apparatus of claim 21 wherein said flip flop means includes: a first delay circuit responsive to the clock pulses for developing first delayed clock pulses; and a first flip flop responsive to the rectangular waveform and the first delayed clock pulses for developing the pulse width modulated signal.
Claim 27
Dependent Claim
75 words
The apparatus of claim 23 wherein said output means includes: a second delay circuit responsive to first delayed clock pulses for developing second delayed clock pulses; a second flip flop responsive to clock pulses, second delayed clock pulses and the pulse width modulated signal for developing output pulses during the first mode of operation; and counting means responsive to the output pulses for generating a digital representation of the amplitude of the input analog current.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-03 | 1979-05-05 | 1979-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-03 | 1983-05-05 | 1983-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-03 | 1987-05-05 | 1987-11-04 | $7700.00 | Window Closed / Lapsed |