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US4763328A
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Viterbi decoder and method for testing the viterbi decoder
Assignee: Fujitsu Ltd
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Filing: 1986-10-16
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Granted: 1988-08-09
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Expires: 2006-10-16
Abstract
Abstract An integrated viterbi decoder structure and method, the viterbi decoder receives test input signals at a distributor, an ACS circuit and a path memory and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder.
Inventors
- 👤 Kaneyasu Shimoda
- 👤 Atsushi Yamashita
- 👤 Tadayoshi Katoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:46
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/01; H03M13/37; H03M13/39; H03M13/41
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
287 words
An integrated viterbi decoder for decoding received code sequences, comprising: input means for receiving test code sequences and for outputting signals varying in accordance with said received test code sequences; distributor means, operatively connected to said input means, for calculating branch metrics and for outputting signals responsive to said calculation; first selector means, operatively connected to receive first control signals, to said input means and to said distributor means, for selectively providing said signals output from said distributor means and from said input means in accordance with said first control signals; ACS means, operatively connected to said input means and to said distributor means, for adding branch metrics in order to generate path metrics, for comparing the generated path metrics, for selecting a maximum likelihood path in accordance with the results of comparing the path metrics, and for outputting signals responsive to said selection; second selector means, operatively connected to receive the first control signal, to said ACS means and to said input means, for selectively providing said signals from said ACS means and from said input means in accordance with the first control signals; path memory means, operatively connected to said ACS means and to said input means, for storing an initial predetermined pattern and for storing transitions in the maximum likelihood path selected by said ACS means; and output means, operatively connected to receive second control signals, to said distributor means, to said ACS means and to said path memory means, for selectively providing said signals output from said distributor means, said ACS means and to said path memory means, for selectively providing said signals output from said distributor means, said ACS means and said path memory means in accordance with said second control signals.
Claim 2
Dependent Claim
287 words
An integrated viterbi decoder for decoding received code sequences, comprising: input means for receiving test code sequences and for outputting signals varying in accordance with said received test code sequences; distributor means, operatively connected to said input means, for calculating branch metrics and for outputting signals responsive to said calculation; first selector means, operatively connected to receive first control signals, to said input means and to said distributor means, for selectively providing said signals output from said distributor means and from said input means in accordance with said first control signals; ACS means, operatively connected to said input means and to said distributor means, for adding branch metrics in order to generate path metrics, for comparing the generated path metrics, for selecting a maximum likelihood path in accordance with the results of comparing the path metrics, and for outputting signals responsive to said selection; second selector means, operatively connected to receive the first control signal, to said ACS means and to said input means, for selectively providing said signals from said ACS means and from said input means in accordance with the first control signals; path memory means, operatively connected to said ACS means and to said input means, for storing an initial predetermined pattern and for storing transitions in the maximum likelihood path selected by said ACS means; and output means, operatively connected to receive second control signals, to said distributor means, to said ACS means and to said path memory means, for selectively providing said signals output from said distributor means, said ACS means and to said path memory means, for selectively providing said signals output from said distributor means, said ACS means and said path memory means in accordance with said second control signals.
Claim 3
Dependent Claim
24 words
An integrated viterbi decoder according to claim 1, wherein said input means includes means for selectively receiving code sequences and said test code sequences.
Claim 4
Independent Claim
100 words
A method for testing an integrated viterbi decoder having a distributor for calculating branch metrics, an ACS circuits for adding the branch metrics to generate path metrics, comparing path metrics and selecting the maximum likelihood path, and a path memory for storing transistions in the maximum likelihood path selected by the ACS circuit, said method comprising the steps of: resetting the ACS circuit and the path memory; applying predetermined test code sequences to the distributor, the ACS circuit and the path memory respectively; selectively providing and sampling the outputs of the distributor, the ACS circuit and the path memory; and
Claim 5
Independent Claim
100 words
A method for testing an integrated viterbi decoder having a distributor for calculating branch metrics, an ACS circuits for adding the branch metrics to generate path metrics, comparing path metrics and selecting the maximum likelihood path, and a path memory for storing transistions in the maximum likelihood path selected by the ACS circuit, said method comprising the steps of: resetting the ACS circuit and the path memory; applying predetermined test code sequences to the distributor, the ACS circuit and the path memory respectively; selectively providing and sampling the outputs of the distributor, the ACS circuit and the path memory; and
Claim 6
Dependent Claim
19 words
comparing the read outputs of the distributor, the ACS circuit and the path memory with predetermined test codes sequences.
Claim 7
Dependent Claim
19 words
comparing the read outputs of the distributor, the ACS circuit and the path memory with predetermined test codes sequences.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |