Nitride-less process for VLSI circuit device isolation

Claim 2

In an integrated circuit fabrication process, a method of forming electrical insulation components in an integrated circuit having a semiconductor substrate, comprising: forming a first insulator layer on said substrate; forming a first mask on said layer to define a pattern of surface areas of said substrate beneath said insulator layer where isolation barrier components are to be formed; introducing impurities into said surface areas to form said isolation barrier components in said substrate subjacent said surface areas; removing said first mask forming a second insulator layer on said first insulator layer; forming a second mask on said second insulator layer to define a pattern of surface areas of said substrate where active device regions are to be formed; and removing said second insulator layer from said substrate according to said second mask pattern to form field isolation insulator components on said substrate.

Claim 3

The method as set forth in claim 1, wherein the step of forming a first mask further comprises: using a nitride-less material to form said first mask.

Claim 4

The method as set forth in claim 2, wherein the step of forming a first mask further comprises: forming a mask of photoresist material, defining a pattern of apertures, on said first insulator layer; and heat treating said mask to cause said photoresist material to flow partially into said apertures, whereby the area defined by said mask is less than the area prior to said heat treating.

Claim 5

The method as set forth in claim 1, wherein said step of removing said first mask further comprises the steps of: etching said insulator layer in accordance with said first mask pattern; removing said mask; and forming a layer of material on said first insulator layer which will have a conformal topography.

Claim 6

The method as set forth in claim 1, wherein said step of forming a first mask further comprises: forming a layer of a first insulator material, having a first etch rate characteristic, on said first insulator layer; etching said layer of first insulator material to define a pattern of apertures superposing said areas; forming a layer of a second insulator material, having a second etch rate characteristic selective over said first etch rate, on said layer of said first insulator material; etching said second insulator material until only aperture lining regions of said second insulator material remain, whereby the area defined by said mask is less than the area defined by said layer of said first insulator material.

Claim 7

The method as set forth in claim 5, wherein said step of forming the first insulator material further comprises: forming the first insulator layer of material selected from a group consisting of silicon dioxide, polysilicon, and silicon nitride.

Claim 8

The method as set forth in claim 6, wherein said step of forming a layer of a second insulator material further comprises: depositing silicon dioxide.

Claim 9

An integrated circuit fabrication process of forming field isolation structures and electrical barrier isolation regions for a silicon-based semiconductor substrate, comprising: forming a first silicon dioxide layer on a major surface of said substrate; forming a first mask of nitride-less material on said first silicon dioxide layer, said first mask having a pattern which defines areas of said surface beneath which said barrier isolation components are to be formed subjacently in said substrate; introducing impurities into said substrate according to said mask pattern to form said barrier isolation components; removing said first mask; forming a second silicon dioxide layer on said first silicon dioxide layer; forming a second mask on said second silicon dioxide layer, said second mask having a pattern which defines areas of said surface, adjacently spaced from said isolation barrier regions, where active device regions of said integrated circuit are to be formed; and etching said second silicon dioxide layer in accordance with said second mask pattern, whereby field oxide isolation structures superposing said electrical barrier isolation regions remain on said surface.

Claim 10

An integrated circuit fabrication process of forming field isolation structures and electrical barrier isolation regions for a silicon-based semiconductor substrate, comprising: forming a first silicon dioxide layer on a major surface of said substrate; forming a first mask of nitride-less material on said first silicon dioxide layer, said first mask having a pattern which defines areas of said surface beneath which said barrier isolation components are to be formed subjacently in said substrate; introducing impurities into said substrate according to said mask pattern to form said barrier isolation components; removing said first mask; forming a second silicon dioxide layer on said first silicon dioxide layer; forming a second mask on said second silicon dioxide layer, said second mask having a pattern which defines areas of said surface, adjacently spaced from said isolation barrier regions, where active device regions of said integrated circuit are to be formed; and etching said second silicon dioxide layer in accordance with said second mask pattern, whereby field oxide isolation structures superposing said electrical barrier isolation regions remain on said surface.

Claim 11

The method as set forth in claim 8, wherein the step of forming a first mask further comprises: forming a mask of photoresist material, having a pattern of apertures, on said first silicon dioxide layer; and heat treating said mask to cause said photoresist material to flow partially into said apertures, whereby each area defined by said mask is less than the area defined prior to said heat treating.

Claim 12

The method as set forth in claim 8, wherein said step of removing said first mask further comprises the steps of: etching said first silicon dioxide layer in accordance with said first mask pattern; removing said mask; and forming a third silicon dioxide layer on said first silicon dioxide layer whereby said third silicon dioxide layer provides alignment marks for subsequent process steps.

Claim 13

The method as set forth in claim 8, wherein said step of forming a first mask further comprises: forming a layer of a first insulator material, having a first etch rate characteristic, on said first silicon dioxide layer; etching said layer of first insulator material to define a pattern of apertures superposing said areas; forming a layer of a second insulator material, having a second etch rate characteristic selective over said first etch rate, on said layer of said first insulator material; etching said second insulator material until only aperture lining regions of said second insulator material remain, whereby the area defined by said mask is less than the area defined by said layer of said first insulator material after said etching of said layer of said first insulator material.