Patent US4761729A successfully refreshed from Google Patents.
US4761729A
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Device for exchanging data between a computer and a peripheral unit having a memory formed by shift registers
Assignee: Individual
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Filing: 1986-01-21
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Granted: 1988-08-02
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Expires: 2006-01-21
Abstract
Abstract This is a device for exchanging data between a computer and a peripheral unit. The data supplied by the computer are words of N binary characters (bits), and the data received by the peripheral unit are words of P bits. The device comprises a memory formed by P shift registers of N bits, an address decoding circuit for addressing the registers during exchanges of data, a control unit receiving from the decoding circuit a signal controlling the shifts in the registers. The registers are connected to the computer to receive P words of N bits which are transferred to the peripheral units. They also enable N words of P bits to be transferred to the computer when the peripheral unit supplies P words of N bits.
Inventors
- 👤 Alain Brion
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:26
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F12/00; G06F12/02; G06F12/04; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018; G06F3/00; G06F3/12; G06F3/1297
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
265 words
A device for exchanging data between a computer and a peripheral unit, the data supplied by the computer being words of N binary characters (bits) and the data received by the peripheral unit being words of P bits, N and P being integers, wherein said device comprises at least one memory formed by P shift registers of N bits, an address decoding circuit connected to the shift registers and the computer for addressing the registers during exchanges of data, a control unit connected to control inputs of the shifts in the registers and to a control output of the decoding circuit to receive from the decoding circuit a signal controlling the shifts in the registers, the shift registers each having N parallel inputs connected to the computer to receive P words of N bits, each register having a series output, the P series outputs of the P registers being connected to inputs of the peripheral unit via a transfer means to transfer thereto the P words of N bits contained in the shift registers, said shift registers also each comprising a series input, the P series inputs of the registers being connected to outputs of the peripheral unit via a bus transfer means to receive N words of P bits, the registers also each having P parallel outputs connected to inputs of the computer to transfer thereto the P words of N bits contained in the shift registers, the bus transfer means connected to the P series inputs and to the peripheral unit permitting an exchange of data between the peripheral unit and the computer.
Claim 2
Independent Claim
265 words
A device for exchanging data between a computer and a peripheral unit, the data supplied by the computer being words of N binary characters (bits) and the data received by the peripheral unit being words of P bits, N and P being integers, wherein said device comprises at least one memory formed by P shift registers of N bits, an address decoding circuit connected to the shift registers and the computer for addressing the registers during exchanges of data, a control unit connected to control inputs of the shifts in the registers and to a control output of the decoding circuit to receive from the decoding circuit a signal controlling the shifts in the registers, the shift registers each having N parallel inputs connected to the computer to receive P words of N bits, each register having a series output, the P series outputs of the P registers being connected to inputs of the peripheral unit via a transfer means to transfer thereto the P words of N bits contained in the shift registers, said shift registers also each comprising a series input, the P series inputs of the registers being connected to outputs of the peripheral unit via a bus transfer means to receive N words of P bits, the registers also each having P parallel outputs connected to inputs of the computer to transfer thereto the P words of N bits contained in the shift registers, the bus transfer means connected to the P series inputs and to the peripheral unit permitting an exchange of data between the peripheral unit and the computer.
Claim 3
Dependent Claim
28 words
A device according to claim 1 wherein the transfer means connecting the P outputs of the registers to inputs of the peripheral unit are formed by a bus.
Claim 4
Dependent Claim
98 words
A device according to claim 1 wherein the transfer means comprise a FIFO memory for recording at least N words of P bits, P inputs of the FIFO memory being connected to the P series outputs of the shift registers and P output of the FIFO memory being connected to the inputs of the peripheral unit, the control unit having at least one output connected to a control input of the FIFO memory to supply thereto a signal fixing the frequency of reception by said FIFO memory of N words of P bits coming from the shift registers.
Claim 5
Dependent Claim
109 words
A device according to claim 1 wherein said bus transfer means comprises a FIFO memory for recording at least N words of P bits, P inputs of said FIFO memory being connected to the outputs of the peripheral unit to receive N words of P bits, and P outputs of said FIFO memory being connected by a bus to the P series inputs of the shift registers, the control unit having at least one output connected to a control input of said FIFO memory to supply thereto a signal fixing the frequency of transmission to the shift registers of N words of P bits contained in said FIFO memory.
Claim 6
Dependent Claim
29 words
A device according to claim 3, wherein the P inputs of the FIFO memory are connected to the P series outputs of the shift registers via a three-state bus.
Claim 7
Dependent Claim
28 words
A device according to claim 4, wherein the bus connecting the outputs of the peripheral unit to the P inputs of said FIFO memory is a three-state bus.
Claim 8
Dependent Claim
37 words
A device according to claim 3 or 4, wherein an input of control unit is connected to a state output of said FIFO memory to receive a signal indicating the state of filling of said FIFO memory.
Claim 9
Independent Claim
37 words
A device according to claims 3 or 4 wherein an input of the computer is connected to a state output of said FIFO memory to receive a signal indicating the state of filling of said FIFO memory.
Claim 10
Dependent Claim
42 words
A device according to claim 1 wherein an input of the computer is connected to an output of the control unit to receive a signal indicating that the shift registers are empty or full, when the words contained therein have been transferred.
Claim 11
Dependent Claim
27 words
A device according to claim 3 or 4 wherein the output of the control unit is connected to the input of said FIFO memory via switching means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |