US4333159A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Combination shift register, counter and memory device
Assignee: Siemens AG
•
Filing: 1979-11-05
•
Granted: 1982-06-01
•
Expires: 1999-11-05
Abstract
Abstract A combination of one or more shift registers with a binary counter and a memory device is disclosed wherein binary information inputs are supplied to the shift register through a plurality of AND gates which also receive inputs from a pulse generator and the output of the shift register is supplied through a second plurality of AND gates to a storage device, and wherein the binary counter supplies inputs to the second plurality of AND gates, and wherein the pulse generator supplies outputs to the shift register, the binary counter and to the first plurality of AND gates. A second embodiment provides a plurality of shift registers which receive outputs from the first shift register and are connected to a plurality of memories through additional AND gates which are controlled by the pulse generator and the associated shift register.
Inventors
- 👤 Klaus D. Bigall
- 👤 Helmut Roesler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:08
CPC Classifications
G; G10; G10H; G10H1/00; G10H1/18; G10H1/182; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
234 words
A digital semiconductor circuit which receives input signals (I, II, III . . . ) for charging a respective memory cell of a clock-controlled shift register (SR) operating in parallel to serial operation, comprising a clock generator (T) producing first and second clock output signals (1, 2), a shift register (SR), a binary digital counter (DZ), said shift register (SR) and said binary counter (DZ) receiving said first clock output signal (1), a plurality of AND gates (U*) receiving the outputs of respective counting stages of said digital counter (DZ), the serial output of said shift register (SR) connected to inputs of all of said AND gates (U*), an address memory (SP) receiving the outputs of said plurality of AND gates (U*) which are connected to the respective memory cell of said address memory (SP) which is designed as a shift register, a second plurality of AND gates (U) receiving a second output of said clock generator (T) as well as said input signals (I, II, III . . . ) and the output of said second plurality of AND gates connected to said shift register and said second output (2) connected as the reset pulse of said binary digital counter (DZ) and said first and second outputs (1, 2) of said clock generator (T) synchronized such that reset of said binary counter occurs only after the complete emptying of said shift register (SR).
Claim 2
Dependent Claim
234 words
A digital semiconductor circuit which receives input signals (I, II, III . . . ) for charging a respective memory cell of a clock-controlled shift register (SR) operating in parallel to serial operation, comprising a clock generator (T) producing first and second clock output signals (1, 2), a shift register (SR), a binary digital counter (DZ), said shift register (SR) and said binary counter (DZ) receiving said first clock output signal (1), a plurality of AND gates (U*) receiving the outputs of respective counting stages of said digital counter (DZ), the serial output of said shift register (SR) connected to inputs of all of said AND gates (U*), an address memory (SP) receiving the outputs of said plurality of AND gates (U*) which are connected to the respective memory cell of said address memory (SP) which is designed as a shift register, a second plurality of AND gates (U) receiving a second output of said clock generator (T) as well as said input signals (I, II, III . . . ) and the output of said second plurality of AND gates connected to said shift register and said second output (2) connected as the reset pulse of said binary digital counter (DZ) and said first and second outputs (1, 2) of said clock generator (T) synchronized such that reset of said binary counter occurs only after the complete emptying of said shift register (SR).
Claim 3
Dependent Claim
89 words
A digital semiconductor circuit according to claim 1, including at least one further shift register (SR*1, SR*2) which are connected to outputs of said shift register (SR) and said clock generator (T), said further shift registers (SR*1, SR*2) connected through a third plurality of AND gates (U**) driven by the second output (2) of said clock generator (T) and at least one further storage device (SP*1, SP*2) connected to said third plurality of AND gates (U**) for further processing the signal (D) obtained from said first shift register (SR).
References Cited (Backward Citations)
US3453551A
Cited
US3531720A
Cited
US3610799A
Cited
US3777278A
Cited
US3898620A
Cited
US4023144A
Cited
US4179747A
Cited
US4203030A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-31 | 1985-11-30 | 1986-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-31 | 1989-11-30 | 1990-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-31 | 1993-11-30 | 1994-06-01 | $7700.00 | Window Closed / Lapsed |