System for transferring bits between a plurality of asynchronous channels and a synchronous channel

Claim 1

A bit transfer system for transferring data bits from each one of a number of asynchronous channels to a synchronous channel, the number of the asynchronous channels not exceeding a predetermined integer K greater than 1, and the number of data bits per data character not exceeding a predetermined integer n greater than 1 for any one of the asynchronous channels, said system comprising: K first circuits respectively including K first terminal memories each having a one-bit capacity, each of said K first circuits comprising means for coupling to an asynchronous channel, means for successively transferring the bits from said asynchronous channel to its terminal memory, and signal generating means for generating a signal upon a bit entering its terminal memory; a circulating intermediate memory comprising K.C sections respectively including K.C data compartments and K.C. auxiliary compartments, C being an integer greater than 1, each data compartment comprising n successive cells for storing a character, each auxiliary compartment comprising j auxiliary cells, j being an integer greater than 1, for storing bits indicating the amount of occupation of the data compartment belonging to the same section; each of said cells having a onebit storage capacity; said circulating intermediate memory comprising an assembly of (n+j) shift registers having successive stages and means for applying thereto the same clock pulses, said assembly of shift registers comprising n successive data shift registers for the circulation of said data compartments and j auxiliary shift registers for the circulation of said auxiliary compartments; an adress circuit fed by said clock pulses, for determining in said intermediate memory K groups of C successive sections respectively including K groups of C successive data compartments and assigning said K groups of data compartments and said K groups of sections to said K first terminal memories respectively through delivering address signals indicative of the position of said groups of sections in said shift registers; a (K+1)th circuit having means for coupling to a synchronous channel, and including a (K+1)th terminal memory having an nbit capacity for storing the characters successively extracted from said intermediate memory, transfer means for receiving each character successively stored in said (K+1)th terminal memory and successively transferring the bits thereof to said synchronous channel, signal generating means for generating signals indicating that said (K+1)th terminal memory is available for receiving a further character, and a timing circuit for determining the time channels respectively assigned to the characters originating from said K first terminal memories respectively, through delivering timing signals indicative of the time intervals respectively allowed for transferring characters from said K groups of data compartments respectively to said (K+1)th terminal memory; auxiliary means coupled to the last two stages of said auxiliary shift registers for delivering auxiliaRy signals indicating whether the data compartment then occupying the penultimate stages of said data shift registers is or is not occupied by a complete character, and which is the first unoccupied cell of the data compartment then occupying the last stages of said data shift registers; and control means, controlled by said address signals, said clock pulses, said auxiliary signals, said timing signals, the signals from said signal generating means of said K first circuits, and the signals from said signal generating means of said (K+1)th circuit, for: -writing bit by bit the bits successively stored in said K first terminal memories respectively, in the groups of data compartments respectively assigned to said K first terminal memories, so that the first available data compartment of a group, in the direction of circulation of the intermediate memory, successively receives the bits of a complete character, each writing-in of a bit in a data compartment occurring upon this data compartment entering the first stages of said data shift registers, and simultaneously modifying the contents of the auxiliary compartment of the section to which this data compartment belongs; - transferring the complete characters successively stored in the first data compartments of said groups to said (K+1)th terminal memory during said time intervals respectively allowed for said groups respectively, each transfer from the first data compartment of a group to said (K+1)th terminal memory occurring upon said data compartment leaving the last stages of said data shift registers, and transferring the contents of each one of the sections of this group other that the first one to the preceding section of this group, this being hereinafter referred to as ''''contents transfer operation.''''