Memory circuit enchancement to stablize the signal lines with additional capacitance

Claim 1

An improvement for monolithic integrated circuits having a voltage level state switching circuit arrangement therein subject to an electrical charge generating disturbances where such voltage level states represent logic signals or data signals, said arrangement comprising at least in part a plurality of signal line pairs including first and second signal line pairs with each member line of said signal line pairs being capable of conducting electrical signals and with each of said first and second signal line pairs having at least one circuit portion electrically connected between its said member lines, including a first pair first circuit portion electrically connected between first signal line pair member lines and a second pair first circuit portion electrically connected between said second signal line pair member lines, such that either of said first and second circuit portions, upon receiving an access signal, can cause a selected one of said member lines connected thereto as aforesaid to be in a selected voltage level state and can cause said other member line connected thereto to be in a different voltage level state, said improvement in combination with the foregoing comprising: a stabilizing capacitance electrically connected through a plurality of unidirectional current conducting means individually to member lines of said plurality of signal line pairs, including being electrically connected through a first unidirectional current conducting means to one of said member lines of said first signal pair and through a second unidirectional current conducting means to that remaining said member line of said first signal line pair, and again through a third unidirectional current conducting means to one of said member lines of said second signal line pair and through a fourth unidirectional current conducting means to that remaining said member line of said second signal line pair.