Analog image memory device using charge transfer

Claim 2

A memory device for storing a video signal in analog form using charge transfer comprising: a memory zone (1) or N lines and M columns of memory points, each memory point being formed by the integration on the same semiconductor substrate of a MIS capacitor (ST) separated from a diode (D) by a screen gate (G), addressing means (RV, RH) connected respectively to each line and each column of memory points for selecting each memory point individually, writing means (T5, VE, R, T1, T2) connected to each memory point for writing in turn in the MIS capacitor of each individual memory point selected by the addressing means a charge amount corresponding to an analog signal (VE) to be stored, and charge reading means (2, RCCD) connected to each column for reading the memory zone line by line after writing.

Claim 3

The memory device as claimed in claim 1, wherein said addressing means comprise means (R, T1, T2) for applying a potential on the MIS capacitors line by line and means for applying a potential on the screen gates column by column.

Claim 4

The memory device as claimed in claim 2, wherein said means for applying a potential on the MIS capacitors line by line comprise a logic shift register (RV) with N outputs, each output being connected to the gate of a MOS transistor (T2) one electrode of which is connected to a load (T2) biased to a high level and to the MIS capacitors (ST) of the same line and the other electrode of which receives the analog signal (VE) to be stored.

Claim 5

The memory device as claimed in claim 2, wherein said means for applying a potential on said screen gates column by column comprise a logic shift register (RH) with M outputs, each output being connected to the gate of a MOS transistor (T3) one electrode of which is connected to a load (T4) imposing a low level potential and to the screen gates of the same column and the other electrode of which receives a high level potential.

Claim 6

The memory device as claimed in claim 1, wherein said writing means are formed by devices allowing charge injection by skimming the potential well created under the MIS capacitors.

Claim 7

The memory device as claimed in claim 5, wherein said writing means comprise MOS transistors (T5) addressing each column of diodes whose gate is connected to a periodic potential enabling the MOS transistors during the writing sequence and one electrode of which receives a periodic signal varying between a high level and a low level at the point frequency.

Claim 8

The memory device as claimed in claim 1, wherein said means for reading the memory zone line by line after writing are formed by a memory of M points, called line memory, each point of which is connected to N diodes (D) of the same and by an analog shift register (R CCD ) receiving in parallel the charges supplied by the line memory and delivering them in series to a reading stage delivering the previously stored analog signal.

Claim 9

The memory device as claimed in claim 7, wherein the line memory is formed by M storage capacities (C), each capacitor being connected on the one hand to the N diodes (D) of the same column through a reading diode (D1) and a passage gate (C1) brought to a high level during the reading sequence and on the other hand to an input of the analog shift register (R CCD ) through a second passage gate (C2) connected to a periodic potential.

Claim 10

The memory device as claimed in claim 7, further comprising means (D', G p , C s ) for injecting drive charges into the line memory.

Claim 11

The memory device as claimed in claim 8, further comprising means (D', G p , C s ) for injecting drive charges into the line memory.

Claim 12

The memory device as claimed in claim 9, wherin a device for injecting a charge in series is associated with the analog shift register.

Claim 13

The memory device as claimed in claim 10, wherein a device for injecting a charge in series is associated with the analog shift register.

Claim 14

The memory device as claimed in claim 1, wherein the analog signal to be stored in an analog signal coded on several levels.

Claim 15

A circulating memory formed by two memory devices as claimed in claim 1, the output of each memory device being connected to the input of the other memory device by means of a device for regenerating the levels.

Claim 16

A memory device for storing a video signal in analog form using charge transfer comprising: a memory zone (1) or N lines and M columns of memory points, each memory point being formed by the integration on the same semiconductor substrate of a MIS capacitor (ST) separated from a diode (D) by a screen gate (G), a logic shift register (RV) with N outputs, each output being connected to the gate of a MOS transistor (T2) one electrode of which is connected to a load (T1) biased to a high level and to the MIS capacitors (ST) of the same line and the other electrode of which receives the analog signal (VE) to be stored, a logic shift register (RH) with M outputs, each output being connected to the gate of a MOS transistor (T3) one electrode of which is connected to a load (T4) imposing a low level potential and to the screen gates of the same column and the other electrode of which receives a high level potential, writing means (T5, VE, R, TI, T2) connected to each memory point for writing in the MIS capacitor of an individual memory point selected by the addressing means a charge amount corresponding to an analog signal (VE) to be stored, and a charge reading means (2, RCCD) connected to each column for reading the memory zone line by line after writing.

Claim 17

A memory device for storing a video signal in analog form using charge transfer comprising: a memory zone (1) or N lines and M columns of memory points, each memory point being formed by the integration on the same semiconductor substrate of a MIS capacitor (ST) separated from a diode (D) by a screen gate (G), a logic shift register (RV) with N outputs, each output being connected to the gate of a MOS transistor (T2) one electrode of which is connected to a load (T1) biased to a high level and to the MIS capacitors (ST) of the same line and the other electrode of which receives the analog signal (VE) to be stored, a logic shift register (RH) with M outputs, each output being connected to the gate of a MOS transistor (T3) one electrode of which is connected to a load (T4) imposing a low level potential and to the screen gates of the same column and the other electrode of which receives a high level potential, writing means (T5, VE, R, TI, T2) connected to each memory point for writing in the MIS capacitor of an individual memory point selected by the addressing means a charge amount corresponding to an analog signal (VE) to be stored, and a charge reading means (2, RCCD) connected to each column for reading the memory zone line by line after writing.

Claim 18

The memory device as claimed in claim 15, wherein said writing means are formed by devices allowing charge injection by skimming the potential well created under the MIS capacitors.

Claim 19

The memory device as claimed in claim 16, wherein said writing means comprise MOS transistors (T5) addressing each column of diodes whose gate is connected to a periodic potential enabling the MOS transistors during the writing sequence and one electrode of which receives a periodic signal varying between a high level and a low level at the point frequency.

Claim 20

The memory device as claimed in claim 15, wherein said means for reading the memory zone line by line after writing are formed by a memory of M points, called line memory, each point of which is connected to N diodes (D) of the same and by an analog shift register (RCCD) receiving in parallel the charges supplied by the line memory and delivering them in series to a reading stage delivering the previously stored analog signal.

Claim 21

The memory device as claimed in claim 18, wherein the line memory is formed by M storage capacities (C), each capacitor being connected on the one hand to the N diodes (D) of the same column through a reading diode (D1) and a passage gate (C1) brought to a high level during the reading sequence and on the other hand to an input of the analog shift register (RCCD) through a second passage gate (C2) connected to a periodic potential.

Claim 22

The memory device as claimed in claim 18, further comprising means (D1, Gp, CS) for injecting drive charges into the line memory.

Claim 23

The memory device as claimed in claim 19, further comprising means (D1, Gp, CS) for injecting drive charges in the line memory.

Claim 24

The memory device as claimed in claim 20, wherein a device for injecting a charge in series is associated with the analog shift register.

Claim 25

The memory device as claimed in claim 21, wherein a device for injecting a charge in series is associated with the analog shift register.

Claim 26

The memory device as claimed in claim 15, wherein the analog signal to be stored is an analog signal coded on several levels.

Claim 27

A circulating memory formed by two memory devices as claimed in claim 16, the output of each memory device being connected to the input of the other memory device by means of a device for regenerating the levels.