Patent US4760544A successfully refreshed from Google Patents.
US4760544A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arithmetic logic and shift device
Assignee: Plessey Semiconductors Ltd
•
Filing: 1986-06-20
•
Granted: 1988-07-26
•
Expires: 2006-06-20
Abstract
Abstract A device which includes an arithmetic logic unit and a data shifter--e.f. a barrel shifter. The outputs of these are cross-coupled to their inputs by separate feedback connections. A third feedback connection is provided between the output of the arithmetic logic unit and another of its inputs. For added versatility in operation, registers at the output of the arithmetic logic unit and the barrel shifter may include each a selectable by-pass and/or additional registers may be included in parallel therewith. The device is reconfigured by the control of input multiplexers interposed between the feedback connections and the arithmetic logic unit and the barrel shifter.
Inventors
- 👤 Kenneth J. Lamb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:56
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
173 words
An arithmetic logic and shift device comprising: an arithmetic logic unit; first and second input multiplexers connected to respective inputs of said arithmetic logic unit; a data shift means; a third input multiplexer connected to an input of said data shift means; first and second data input ports connected respectively to an input of the first input multiplexer and to an input of the third input multiplexer; a first connective feedback path connected to the third input multiplexer to feedback data output from the arithmetic logic unit; a second and independent connective feedback path connected to the second input multiplexer to feedback data output from the data shift means; a third and independent connective feedback path connected to the first input multiplexer to feedback only data output from the arithmetic logic unit; a data output port; and an output multiplexer, connected at respective inputs to receive data from the arithmetic logic unit and from said data shift mean, and connected at output to the data output port to select and pass data thereto.
Claim 2
Dependent Claim
173 words
An arithmetic logic and shift device comprising: an arithmetic logic unit; first and second input multiplexers connected to respective inputs of said arithmetic logic unit; a data shift means; a third input multiplexer connected to an input of said data shift means; first and second data input ports connected respectively to an input of the first input multiplexer and to an input of the third input multiplexer; a first connective feedback path connected to the third input multiplexer to feedback data output from the arithmetic logic unit; a second and independent connective feedback path connected to the second input multiplexer to feedback data output from the data shift means; a third and independent connective feedback path connected to the first input multiplexer to feedback only data output from the arithmetic logic unit; a data output port; and an output multiplexer, connected at respective inputs to receive data from the arithmetic logic unit and from said data shift mean, and connected at output to the data output port to select and pass data thereto.
Claim 3
Dependent Claim
16 words
A device, as claimed in claim 1, wherein the data shift means is a barrel shifter.
Claim 4
Dependent Claim
25 words
A device, as claimed in claim 1, wherein an output register is interposed between the arithmetic logic unit and the first and third feedback paths.
Claim 5
Dependent Claim
16 words
A device, as claimed in claim 3, wherein the output register is provided with a by-pass.
Claim 6
Dependent Claim
22 words
A device, as claimed in claim 3, wherein at least one additional output register is connected in parallel to said output register.
Claim 7
Dependent Claim
23 words
A device, as claimed in claim 1, wherein an output register is interposed between the data shift means and the second feedback path.
Claim 8
Dependent Claim
16 words
A device, as claimed in claim 6, wherein the output register is provided with a by-pass.
Claim 9
Dependent Claim
22 words
A device, as claimed in claim 6, wherein at least one additional output register is connected in parallel to said output register.
Claim 10
Dependent Claim
212 words
An arithmetic logic and shift device comprising: an arithmetic logic unit; first and second input multiplexers connected to respective inputs of said arithmetic logic unit; first and second output registers connected in parallel to an output of the arithmetic logic unit; a barrel shifter; a third input multiplexer connected to an input of said barrel shifter; first and second data input ports connected respectively to an input of the first input multiplexer and to an input of the third multiplexer; third and fourth output registers connected in parallel to an output of the barrel shifter; a first connective feedback path connected between the third input multiplexer and the first and second output registers; a second and independent feedback path connected between the second input multiplexer and the third and fourth output registers; a third and independent feedback path connected between the first input multiplexer and the first and second output registers; a first data input register connected to the first input multiplexer; a second data input register connected to the both second and third input multiplexer; an output connected at respective inputs to the first and second, third and fourth, output registers; an output port; and an output enable gate connected between the output port and an output of the output multiplexer.
Claim 11
Dependent Claim
212 words
An arithmetic logic and shift device comprising: an arithmetic logic unit; first and second input multiplexers connected to respective inputs of said arithmetic logic unit; first and second output registers connected in parallel to an output of the arithmetic logic unit; a barrel shifter; a third input multiplexer connected to an input of said barrel shifter; first and second data input ports connected respectively to an input of the first input multiplexer and to an input of the third multiplexer; third and fourth output registers connected in parallel to an output of the barrel shifter; a first connective feedback path connected between the third input multiplexer and the first and second output registers; a second and independent feedback path connected between the second input multiplexer and the third and fourth output registers; a third and independent feedback path connected between the first input multiplexer and the first and second output registers; a first data input register connected to the first input multiplexer; a second data input register connected to the both second and third input multiplexer; an output connected at respective inputs to the first and second, third and fourth, output registers; an output port; and an output enable gate connected between the output port and an output of the output multiplexer.
Claim 12
Dependent Claim
39 words
A device, as claimed in claim 9, wherein the second input register is connected to all three first, second, and third, input multiplexers; and, the third and fourth output registers are connected to both first and second input multiplexers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |