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EP0042452A1
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EP
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Signal processor computing arrangement and method of operating said arrangement
Assignee: International Business Machines Corp
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Filing: 1980-06-24
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Granted: —
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Expires: 2000-06-24
Abstract
Abstract In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.
Inventors
- 👤 Pierre Chevillat
- 👤 Dieter Maiwald
- 👤 Hans Peter Käser
- 👤 Gottfried Ungerböck
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 08:31
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; G; G06; G06F; G06F17/00; G06F17/10; G06F17/15; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
124 words
Signal processor computing arrangement comprising an arith- metid unit (11) having two inputs (13, 15) and an output (17), for performing at least add and subtract operations, and a multiplier unit (21) operating simultaneously with said arithmetic unit, characterized by - two accumulator registers (37, 41) connected to said arithmetic unit and being selectively loadable from said arithmetic unit output, - two input registers (53, 57) connected to the two inputs of said multiplier unit and being selectively-loadable from a data source (51), and a multiplier output register (35), and - means for selectively gating data from said accumulator registers to one of said arithmetic unit inputs, and for gating data from said multiplier output register to the other of said arithmetic unit inputs.
Claim 2
Dependent Claim
124 words
Signal processor computing arrangement comprising an arith- metid unit (11) having two inputs (13, 15) and an output (17), for performing at least add and subtract operations, and a multiplier unit (21) operating simultaneously with said arithmetic unit, characterized by - two accumulator registers (37, 41) connected to said arithmetic unit and being selectively loadable from said arithmetic unit output, - two input registers (53, 57) connected to the two inputs of said multiplier unit and being selectively-loadable from a data source (51), and a multiplier output register (35), and - means for selectively gating data from said accumulator registers to one of said arithmetic unit inputs, and for gating data from said multiplier output register to the other of said arithmetic unit inputs.
Claim 3
Dependent Claim
85 words
Computing arrangement in accordance with claim 1, characterized in that said multiplier unit (21) is a combinatorial logic network partitioned into at least two sections (29, 31), a pipeline register (33) being provided between subsequent sections so that in each one of successive operating cycles, the first section (29) operates on data bits representing operands available at the two multiplier inputs (23, 25), while each subsequent section (31) operates independently on data bits representing an intermediate multiplication result stored in the preceding pipeline register (33).
Claim 4
Dependent Claim
112 words
Computing arrangement in accordance with claim 1, characterized in that said multiplier unit (21) is a logic network partitioned into two subsequent sections (29, 31) with an intermediate pipeline register (33) being connected between the first and the second section, and that after each of successive operating cycles, the first section (29) furnishes a bit field to said pipeline register representing an intermediate multiplication result for two operands that were available at the multiplier inputs (23, 25) during that cycle, while the second section (31) provides a final result at the multiplier output (27), which is the product of two operands that were available at the multiplier inputs during the previous cycle.
Claim 5
Dependent Claim
46 words
Computing arrangement in accordance with claim 1, characterized in that said selective gating means (61, 63) are also connected to the outputs of said input registers (53, 57) and thus can also selectively gate data from said input registers to said arithmetic unit inputs (13, 15).
Claim 6
Dependent Claim
39 words
Computing arrangement in accordance with claim 1, characterized in that further gating means (45) are provided for selectively gating data from either one of said two accumulator registers (37, 41) to a common output (49) of said computing arrangement.
Claim 7
Dependent Claim
109 words
Method of operating a computing arrangement in accordance with claim 1, for separately generating two sums of two series of products with overlapping sets of operands, characterized in that in successive operation cycles - said two accumulator registers (37, 41) are alternatingly selected for gating their content to said one arithmetic unit input (15) by said gating means (63) and for being loaded with a result from said arithmetic unit output (17), while the content of the respective other accumulator register remains unchanged, and - said two input registers (53, 57) are alternatingly loaded with a new operand, while the content of the respective other input register remains unchanged.
Claim 8
Dependent Claim
53 words
Method in accordance with claim 6, characterized in that operands loaded into one (53) of said input registers in every other cycle are taken from a first set of variables, and that operands loaded into the other (57) of said input registers in the alternate cycles are taken from another set of variables.
References Cited (Backward Citations)
DE2636028A1
Cited
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