Clock signal generating circuit

Claim 1

A clock signal generating circuit for a semiconductor integrated circuit comprising: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a ground side power source line; a capacitor connected between a gate of said first N-channel transistor and a gate of said P-channel transistor, said gate of said P-channel transistor receiving a first clock signal input; a second N-channel transistor connected between a common connection point of said P-channel transistor and said first N-channel transistor and said gate of said first N-channel transistor, a node being positioned between said second N-channel transistor and the gate of said first N-channel transistor, and a second clock signal being applied to a gate of said second N-channel transistor; a bootstrap capacitor connected to said common connection point on one end thereof and receiving a third clock signal at another end thereof; and wherein said first clock signal is applied to said P-channel transistor to render said P-channel transistor non-conductive and said first N-channel transistor conductive, respectively, then said second clock signal is applied to said second N-channel transistor to render said second N-channel transistor conductive, and subsequently said third clock signal is applied to said bootstrap capacitor in order to pull down the potential of said common connection point.