US4636657A
Expired / Lapsed
US
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High speed CMOS clock generator
Assignee: Texas Instruments Inc
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Filing: 1984-08-29
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Granted: 1987-01-13
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Expires: 2004-08-29
Abstract
Abstract A -CMOS clock generator circuit is controlled by two clocks, one always going high before the other when entering an active cycle, and always going low before the other in entering a precharge cycle; this one clock precharges a capacitor through a P-channel transistor, and holds a drive node discharged. Two sets of semi-connected N-channel output transistors are used, with the gates of the top two driven by the drive node, and the gates of the bottom two driven by a CMOS inverter which has the second clock as its input. The inverter output also drives the gate of a P-channel transistor between the capacitor and the drive node. Another P-channel transistor with the first clock on its gate couples the drive node to the intermediate node of the first output pair. The second clock transfers the charge from the capacitor to the drive node, which also causes the capacitor to boot the drive node above the supply. When the first clock goes low it discharges the booted node to the supply rather than to ground.
Inventors
- 👤 Chitranjan Reddy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
241 words
A clock circuit comprising: first and second clock voltages each switching between zero in a precharge cycle and to a supply voltage in an active cycle, an inverter having a pair of inverter transistors with source-to-drain paths connected in series between a voltage supply and ground, the gates of said transistors being coupled to said second clock voltage, the juncture of said transistors providing a first control node, first and second pairs of output transistors, the source-to-drain paths of the first pair being separately connected between ground and a second control node and an output node, respectively, the gates of the first pair of output transistors connected in common to said first control node, the source-to-drain paths of the second pair being separately connected between said supply and said second control node and said output node, respectively, the gates of the second pair of transistors connected in common to a driver node, a first transistor having its source-to-drain path connected between said supply and a charge node; a second transistor having its source-to-drain path connected between said charge node and said driver node; a third transistor having its source-to-drain path connected between said driver node and said second control node; the gates of said first and third transistors being connected to said first clock voltage; the gate of said second transistor being connected to said first control node; and a capacitor connected between said second control node and said charge node.
Claim 2
Dependent Claim
241 words
A clock circuit comprising: first and second clock voltages each switching between zero in a precharge cycle and to a supply voltage in an active cycle, an inverter having a pair of inverter transistors with source-to-drain paths connected in series between a voltage supply and ground, the gates of said transistors being coupled to said second clock voltage, the juncture of said transistors providing a first control node, first and second pairs of output transistors, the source-to-drain paths of the first pair being separately connected between ground and a second control node and an output node, respectively, the gates of the first pair of output transistors connected in common to said first control node, the source-to-drain paths of the second pair being separately connected between said supply and said second control node and said output node, respectively, the gates of the second pair of transistors connected in common to a driver node, a first transistor having its source-to-drain path connected between said supply and a charge node; a second transistor having its source-to-drain path connected between said charge node and said driver node; a third transistor having its source-to-drain path connected between said driver node and said second control node; the gates of said first and third transistors being connected to said first clock voltage; the gate of said second transistor being connected to said first control node; and a capacitor connected between said second control node and said charge node.
Claim 3
Dependent Claim
18 words
A circuit according to claim 1 wherein said inverter transistors include a P-channel transistor and an N-channel transistor.
Claim 4
Dependent Claim
21 words
A circuit according to claim 1 wherein said output transistors are N-channel; and said first, second and third transistors are P-channel.
Claim 5
Dependent Claim
19 words
A circuit according to claim 1 wherein said first clock voltage rises or falls before said second clock voltage.
Claim 6
Dependent Claim
248 words
A clock circuit comprising: first and second clock voltages each switching between zero in a precharge cycle and to a supply voltage in an active cycle, a CMOS inverter having a pair of inverter transistors with source-to-drain paths connected in series between a voltage supply and ground, the gates of such transistors being coupled to said second clock voltage, the juncture of such transistors providing a first control node, first and second pairs of N-channel output transistors, the source-to-drain paths of the first pair being connected separately between said ground and a second control node and an output node, respectively, the gates of the first pair of output transistors connected in common to said first control node, the source-to-drain paths of the second pair being separately connected between said supply and said second control node and said output node, respectively, the gates of the second pair of transistors connected in common to a driver node, a first P-channel transistor having its source-to-drain path connected between said supply and a charge node; a P-channel second transistor having its source-to-drain path connected between said charge node and said driver node; a third P-channel transistor having its source-to-drain path connected between said driver node and said second control node; the gates of said first and third P-channel transistor being connected to said first clock voltage; the gate of said second transistor being connected to said first control node; and a capacitor connected between said second control node and said charge node.
Claim 7
Dependent Claim
248 words
A clock circuit comprising: first and second clock voltages each switching between zero in a precharge cycle and to a supply voltage in an active cycle, a CMOS inverter having a pair of inverter transistors with source-to-drain paths connected in series between a voltage supply and ground, the gates of such transistors being coupled to said second clock voltage, the juncture of such transistors providing a first control node, first and second pairs of N-channel output transistors, the source-to-drain paths of the first pair being connected separately between said ground and a second control node and an output node, respectively, the gates of the first pair of output transistors connected in common to said first control node, the source-to-drain paths of the second pair being separately connected between said supply and said second control node and said output node, respectively, the gates of the second pair of transistors connected in common to a driver node, a first P-channel transistor having its source-to-drain path connected between said supply and a charge node; a P-channel second transistor having its source-to-drain path connected between said charge node and said driver node; a third P-channel transistor having its source-to-drain path connected between said driver node and said second control node; the gates of said first and third P-channel transistor being connected to said first clock voltage; the gate of said second transistor being connected to said first control node; and a capacitor connected between said second control node and said charge node.
Claim 8
Dependent Claim
27 words
A circuit according to claim 5 wherein said first clock voltage makes a transition from ground to supply voltage while the second clock voltage is at ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-12 | 1990-07-14 | 1991-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-12 | 1994-07-14 | 1995-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-12 | 1998-07-14 | 1999-01-13 | $7700.00 | Window Closed / Lapsed |