US4759041A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Local area network control system synchronization with phase-lock loop
Assignee: Lockheed Martin Corp
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Filing: 1987-02-19
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Granted: 1988-07-19
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Expires: 2007-02-19
Abstract
Abstract A local area network packet receiving system synchronizes the passage of packets through a receive buffer through a synchronizing circuit which supplies clock pulses to the receive buffer. The clock system utilizes a sensing circuit that senses the rate at which packets are being stored in the receive buffer. A master oscillator provides a reference signal and a rate control circuit coupled to the sensing circuit controls the rate at which the clock pulses are supplied to the receive buffer. A programmable timer supplies timing pulses out of the control of the rate control circuit. A phase-lock-loop having first and second comparison inputs is coupled to the programmable timer to receive the timing pulses on the first comparison input and to the master oscillator to receive a reference signal on the second comparsion input. A pulse circuit is coupled to the phase-lock-loop to supply clock pulses which are derived from the output of the phase-lock-loop, and which have a pulse repetition rate that matches the rate at which packets are being stored in the receive buffer.
Inventors
- 👤 Steven C. Anderson
- 👤 Joseph Pobiel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:57
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0632; G; G06; G06F; G06F5/00; G06F5/06; G06F2205/00; G06F2205/06; G06F2205/061
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
190 words
In a local area network packet receiving system comprising receive buffer means, and clock means for synchronizing the passage of packets through said receive buffer means, the improvement comprising output means for supplying clock pulses to said receive buffer means and clock means which comprises sensing means for sensing the rate at which said packets are being stored in said receive buffer means, master oscillator means for providing a reference signal, rate control means coupled to said sensing means for controlling the rate at which said output means supplies said clock pulses, and programmable timing means which supplies timing pulses under the control of said rate control means, wherein said output means comprises phase-lock loop means having first and second comparison inputs coupled to said programmable timing means to receive said timing pulses on said first comparison input and to said master oscillator means to receive said reference signal on said second comparison input and pulse means for supplying clock pulses derived from the output of said phase-lock loop means which have pulse repetition rates that match the rate at which packets are being stored in said receive buffer means.
Claim 2
Dependent Claim
190 words
In a local area network packet receiving system comprising receive buffer means, and clock means for synchronizing the passage of packets through said receive buffer means, the improvement comprising output means for supplying clock pulses to said receive buffer means and clock means which comprises sensing means for sensing the rate at which said packets are being stored in said receive buffer means, master oscillator means for providing a reference signal, rate control means coupled to said sensing means for controlling the rate at which said output means supplies said clock pulses, and programmable timing means which supplies timing pulses under the control of said rate control means, wherein said output means comprises phase-lock loop means having first and second comparison inputs coupled to said programmable timing means to receive said timing pulses on said first comparison input and to said master oscillator means to receive said reference signal on said second comparison input and pulse means for supplying clock pulses derived from the output of said phase-lock loop means which have pulse repetition rates that match the rate at which packets are being stored in said receive buffer means.
Claim 3
Dependent Claim
38 words
In a local area network receiving system as claimed in claim 1 the improvement comprising digital-to-analog converter means coupled to said receive buffer means to receive said packets and to said output means to receive said clock pulses.
Claim 4
Independent Claim
219 words
A system to control the clocking of a receive buffer in a local area network in which a first digital signal is applied on one input of a phase-locked loop means and a second digital signal is supplied on a second input of said phase-locked loop means, and an output of said phase-locked loop means supplies a signal representative of the phase difference between said first and second signals, wherein the system comprises first signal means for supplying said first digital signal at a predetermined frequency coupled to said first input, programmable frequency divider means coupled to said output to receive said output signals and to said second input of said phase-locked loop means in order to provide a programmed frequency divided signal as said second digital signal thereto, coupling means coupled to said output to supply a clock output signal to said receive buffer, and control means for controlling the frequency of said programmable frequency divider means coupled to said programmable frequency divider means, wherein said control means comprises a sensing circuit which is coupled to said receive buffer to sense the rate at which data packets are stored in the receive buffer so that the clock output signal from said coupling means controls the clocking of information through the receive buffer in response to said sensing means.
Claim 5
Independent Claim
219 words
A system to control the clocking of a receive buffer in a local area network in which a first digital signal is applied on one input of a phase-locked loop means and a second digital signal is supplied on a second input of said phase-locked loop means, and an output of said phase-locked loop means supplies a signal representative of the phase difference between said first and second signals, wherein the system comprises first signal means for supplying said first digital signal at a predetermined frequency coupled to said first input, programmable frequency divider means coupled to said output to receive said output signals and to said second input of said phase-locked loop means in order to provide a programmed frequency divided signal as said second digital signal thereto, coupling means coupled to said output to supply a clock output signal to said receive buffer, and control means for controlling the frequency of said programmable frequency divider means coupled to said programmable frequency divider means, wherein said control means comprises a sensing circuit which is coupled to said receive buffer to sense the rate at which data packets are stored in the receive buffer so that the clock output signal from said coupling means controls the clocking of information through the receive buffer in response to said sensing means.
Claim 6
Dependent Claim
222 words
The use of a system to control the clocking of a receive buffer in a local area network in which a first digital signal is applied on one input of a phase-locked loop means and a second digital signal is supplied on a second input of said phase-locked loop means, and an output of said phase-locked loop means supplies a signal representative of the phase difference between said first and second signals, wherein the system comprises first signal means for supplying said first digital signal at a predetermined frequency coupled to said first input, programmable frequency divider means coupled to said output to receive said output signals and to said second input of said phase-locked loop means in order to provide a programmed frequency divided signal as said second digital signal thereto, coupling means coupled to said output to supply a clock output signal to said receive buffer, and control means for controlling the frequency of said programmable frequency divider means coupled to said programmable frequency divider means, wherein said control means comprises a sensing circuit which is coupled to said receive buffer to sense the rate at which data packets are stored in the receive buffer so that the clock output signal from said coupling means controls the clocking of information through the receive buffer in response to said sensing means.
Claim 7
Dependent Claim
222 words
The use of a system to control the clocking of a receive buffer in a local area network in which a first digital signal is applied on one input of a phase-locked loop means and a second digital signal is supplied on a second input of said phase-locked loop means, and an output of said phase-locked loop means supplies a signal representative of the phase difference between said first and second signals, wherein the system comprises first signal means for supplying said first digital signal at a predetermined frequency coupled to said first input, programmable frequency divider means coupled to said output to receive said output signals and to said second input of said phase-locked loop means in order to provide a programmed frequency divided signal as said second digital signal thereto, coupling means coupled to said output to supply a clock output signal to said receive buffer, and control means for controlling the frequency of said programmable frequency divider means coupled to said programmable frequency divider means, wherein said control means comprises a sensing circuit which is coupled to said receive buffer to sense the rate at which data packets are stored in the receive buffer so that the clock output signal from said coupling means controls the clocking of information through the receive buffer in response to said sensing means.
References Cited (Backward Citations)
US3988696A
Cited
US4270183A
Cited
US4181975A
Cited
US4330856A
Cited
US4280104A
Cited
US4280099A
Cited
US4363002A
Cited
US4400817A
Cited
US4451930A
Cited
US4679003A
Cited
US4654859A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-19 | 1992-01-18 | 1992-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-19 | 1996-01-18 | 1996-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-19 | 2000-01-18 | 2000-07-19 | $7700.00 | Window Closed / Lapsed |