Patent US4758305A successfully refreshed from Google Patents.
US4758305A
Expired / Lapsed
US
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Contact etch method
Assignee: Texas Instruments Inc
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Filing: 1986-03-11
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Granted: 1988-07-19
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Expires: 2006-03-11
Abstract
Abstract A method for patterning small-geometry contacts with sloped sidewalls in integrated circuit fabrication. A multilayer resist process is used, and the spacer layer is undercut by overexposure and overdevelopment at the pattern transfer stage. This provides a cantilever etch mask structure, without the need to use any hardmask layers.
Inventors
- 👤 Thomas D. Bonifield
- 👤 Vic B. Marriott
- 👤 Rhett B. Jucha
- 👤 Monte A. Douglas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:18
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P50/73; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/952
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
253 words
A method of fabricating integrated circuits, comprising the steps of: (a) providing a partially fabricated integrated circuit structure having a dielectric thereon overlying predetermined contact hole locations; (b) coating a photosensitive spacer layer onto said partially fabricated integrated circuit structure; (c) coating a photosensitive top layer over said spacer layer; (d) exposing said top layer at a first wavelength to which said top layer is photosensitive and said spacer layer is not photosensitive to define said predetermined contact hole locations, and (e) developing said top layer to define apertures over said contact hole locations in said top layer; (f) exposing said top layer and said spacer layer at a second wavelength to which said top layer is substantially opaque and said spacer layer is photosensitive to expose said spacer layer in accordance with said apertures in said top layer, said second wavelength exposing step being performed for at least twice the duration required to completely expose portions of said spacer layer beneath the center of said apertures in said top layer, and (g) developing said top spacer layer so that said spacer layer is undercut to define apertures in said spacer layer which underlie said apertures in said top layer but have a minimum width more than twice the minimum width of said apertures in said top layer; and (h) dry etching said dielectric with said patterned top layer and spacer layer thereover, whereby said dielectric is etched to have contact holes in said predetermined pattern, and said contact holes have sloped sidewalls.
Claim 2
Independent Claim
253 words
A method of fabricating integrated circuits, comprising the steps of: (a) providing a partially fabricated integrated circuit structure having a dielectric thereon overlying predetermined contact hole locations; (b) coating a photosensitive spacer layer onto said partially fabricated integrated circuit structure; (c) coating a photosensitive top layer over said spacer layer; (d) exposing said top layer at a first wavelength to which said top layer is photosensitive and said spacer layer is not photosensitive to define said predetermined contact hole locations, and (e) developing said top layer to define apertures over said contact hole locations in said top layer; (f) exposing said top layer and said spacer layer at a second wavelength to which said top layer is substantially opaque and said spacer layer is photosensitive to expose said spacer layer in accordance with said apertures in said top layer, said second wavelength exposing step being performed for at least twice the duration required to completely expose portions of said spacer layer beneath the center of said apertures in said top layer, and (g) developing said top spacer layer so that said spacer layer is undercut to define apertures in said spacer layer which underlie said apertures in said top layer but have a minimum width more than twice the minimum width of said apertures in said top layer; and (h) dry etching said dielectric with said patterned top layer and spacer layer thereover, whereby said dielectric is etched to have contact holes in said predetermined pattern, and said contact holes have sloped sidewalls.
Claim 3
Dependent Claim
56 words
The method of claim 1, further comprising the additional step, subsequent to said etching step (h), of (i) coating a metal overall, whereby said metal makes contact to portions of said partially fabricated integrated circuit structure at the bottoms of said contact holes without open circuits in said metal near the sidewalls of said contact holes.
Claim 4
Dependent Claim
53 words
The method of claim 1, further comprising the additional step, prior to said coating step (c) and subsequent to said coating step (b), of (j) coating an antireflective coating over said spacer layer; (e) wherein said developing step (e) also removes portions of said antireflective coating beneath said apertures in said top layer.
Claim 5
Dependent Claim
39 words
The method of claim 1, wherein said developing step (g) is performed for at least twice the duration required to completely remove exposed portions of said spacer layer directly beneath the centers of said apertures in said top layer.
Claim 6
Dependent Claim
14 words
The method of claim 1, wherein said spacer layer consists essentially of polymethylmethacrylate (PMMA).
Claim 7
Dependent Claim
43 words
The method of claim 1, wherein said step (c) of coating on said spacer layer applies said spacer layer in a planarizing fashion, whereby said top layer is more planar than portions of said partially fabricated integrated circuit structure underlying said spacer layer.
Claim 8
Dependent Claim
36 words
The method of claim 1, wherein said etching step (h) exposes portions of said partially fabricated integrated circuit structure under said dielectric which include both a substrate and an insulated conductive line running over said substrate.
Claim 9
Dependent Claim
52 words
The method of claim 1, wherein said etching step (h) exposes portions of said partially fabricated integrated circuit structure under said dielectric which include both a first insulated conductive line running over a substrate and also a second insulated conductive line running over said first insulated conductive line and over said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-19 | 1992-01-18 | 1992-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-19 | 1996-01-18 | 1996-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-19 | 2000-01-18 | 2000-07-19 | $7700.00 | Window Closed / Lapsed |