Sample clock signal generator circuit

Claim 2

Apparatus for outputting to a terminal a signal that is phase synchronized with an external signal, said external signal being received from an external source of signals, said apparatus comprising means for receiving said external signal, means for receiving a primary signal from a signal generator, means for generating a series of time-separated signals from said primary signal, means responsive to receipt of said external signal for generating a signal substantially representative of said external signal, said generated signal having a predetermined transition synchronized with a predetermined transition of said primary signal, and means responsive to said synchronized transition for selecting one of said series of signals as a function of said synchronized transition and for outputting said selected signal as said phase-synchronized signal.

Claim 3

The apparatus set forth in claim 1 wherein the frequency of said primary signal is a predetermined multiple of the frequency of each of said series of time-separated signals.

Claim 4

The apparatus set forth in claim 1 wherein said time separation is substantially equal, to the period of said primary signal.

Claim 5

The apparatus of claim 2 wherein said means for generating said series of signals includes means for dividing the frequency of said primary signal by at least said predetermined multiple to generate a secondary signal and for serially replicating said secondary signal to generate said series of signals.

Claim 6

Apparatus comprising means for receiving a repetitive primary signal of a predetermined frequency from a signal generator. means for receiving an external signal from a source of signals, means responsive to receipt of said primary signal for generating a series of time-separated signals and respective addresses from said primary signal, and means responsive to receipt of said external signal and said primary signal for generating a signal having a predetermined transition synchronized with a predetermined transition of said primary signal and for outputting to a terminal that one of said series of signals whose respective address occurs during said synchronized transition.

Claim 7

Apparatus comprising means for receiving a repetitive primary signal of a predetermined frequency from a signal generator. means for receiving an external signal from a source of signals, means responsive to receipt of said primary signal for generating a series of time-separated signals and respective addresses from said primary signal, and means responsive to receipt of said external signal and said primary signal for generating a signal having a predetermined transition synchronized with a predetermined transition of said primary signal and for outputting to a terminal that one of said series of signals whose respective address occurs during said synchronized transition.

Claim 8

The signal generator set forth in claim 5 wherein the frequency of said primary signal is a predetermined multiple of the frequency of each of said series of signals.

Claim 9

The signal generator of claim 6 wherein said means for generating said series of signals includes means for dividing the frequency of said primary signal by at least said predetermined multiple to generate a secondary signal and for serially replicating said secondary signal to generate said series of signals, said series of signals being time separated from one another and said time seperation being substantially equal to the period of said primary signal.

Claim 10

The signal generator set forth in claim 5 wherein said means for generating said primary signal includes a programmable phase-locked loop frequency synthesizer circuit having a voltage controlled oscillator and a reference oscillator.

Claim 11

Apparatus for generating a sample clock signal, said sample clock signal having a predetermined frequency and being phase synchronized with an external signal, said apparatus comprising means for receiving said external signal, means for receiving frequency programming instructions from an external source of such instructions and for generating a first signal having a frequency defined by said instructions, said frequency of said first signal being a predetermined multiple of the frequency of said sample clock signal, means responsive to said first signal for generating a second signal and a series of addresses, means responsive to said first and second signals for generating a series of time-separated signals each having a frequency substantially equal to the predetermined frequency of said sample clock signal, said series of timeseparated signals being associated with respective ones of said addresses, and means responsive to said external signal for generating a signal substantially a replica of said external signal and having a trailing transition synchronized with a predetermined transition of said first signal and for outputting as said sample clock signal that one of said series of signals whose respective one of said addresses occurs during said trailing transition.

Claim 12

Apparatus for generating a sample clock signal, said sample clock signal having a predetermined frequency and being phase synchronized with an external signal, said apparatus comprising means for receiving said external signal, means for receiving frequency programming instructions from an external source of such instructions and for generating a first signal having a frequency defined by said instructions, said frequency of said first signal being a predetermined multiple of the frequency of said sample clock signal, means responsive to said first signal for generating a second signal and a series of addresses, means responsive to said first and second signals for generating a series of time-separated signals each having a frequency substantially equal to the predetermined frequency of said sample clock signal, said series of timeseparated signals being associated with respective ones of said addresses, and means responsive to said external signal for generating a signal substantially a replica of said external signal and having a trailing transition synchronized with a predetermined transition of said first signal and for outputting as said sample clock signal that one of said series of signals whose respective one of said addresses occurs during said trailing transition.