Patent US4752907A successfully refreshed from Google Patents.
US4752907A
Expired / Lapsed
US
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Integrated circuit scanning apparatus having scanning data lines for connecting selected data locations to an I/O terminal
Assignee: Fujitsu IT Holdings Inc
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Filing: 1986-06-30
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Granted: 1988-06-21
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Expires: 2006-06-30
Abstract
Abstract A scan apparatus provides an interface and control signals between a secondary computer and data locations in a host computer. The scan apparatus functions independently of the normal operation of the host computer. Scan-out is performed transparently to the operation of the host computer. The host computer is constructed using circuits on semiconductor chips. The semiconductor chips are organized in blocks. Chips within each block include scan apparatus which controls the scan operations in connection with that chip. The scan apparatus in each chip is connected through two I/O pins to a clock line and to a bidirectional scan data line. The scan apparatus on each chip includes a multimode sequencer so that each chip in each block can be independently performing scan sequences. The block scan apparatus and the secondary computer perform the functions of requesting a scan sequence for transmitting the scan data.
Inventors
- 👤 Stephen S. C. Si
- 👤 James B. Shackleford
- 👤 Daryl H. Allred
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/2733; G06F11/2268
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
226 words
In an integrated circuit having a normal function performing sequential logic, data locations having connections for use in execution of the normal function and a plurality of input-output terminals coupled to the circuit, an apparatus for scanning the contents of the data locations independent of the connections for use in execution of the normal function comprising: data line means, in communication with a first of the input-output terminals and the data locations, for selectively connecting the data locations to the first input-output terminal across connections separate from the connections for use in execution of the normal function; sequencer means for generating scan sequence signals identifying data locations to be scanned, wherein a second of the input-output terminals is connected to receive a scan clock signal, and the sequencer means is responsive to the scan clock signal for controlling the timing of the generation of the scan sequence signals; decoder means, in communication with the data line means and the sequencer means and responsive to the scan sequence signals, for controlling the selective connection of the data line means to the data locations identified by the scan sequence signals; and control logic, in communication with the sequencer means and connected to the first input-output terminal for receiving control input signals and to the second input-output terminal for receiving the scan clock signal, for controlling the sequencer means.
Claim 2
Dependent Claim
226 words
In an integrated circuit having a normal function performing sequential logic, data locations having connections for use in execution of the normal function and a plurality of input-output terminals coupled to the circuit, an apparatus for scanning the contents of the data locations independent of the connections for use in execution of the normal function comprising: data line means, in communication with a first of the input-output terminals and the data locations, for selectively connecting the data locations to the first input-output terminal across connections separate from the connections for use in execution of the normal function; sequencer means for generating scan sequence signals identifying data locations to be scanned, wherein a second of the input-output terminals is connected to receive a scan clock signal, and the sequencer means is responsive to the scan clock signal for controlling the timing of the generation of the scan sequence signals; decoder means, in communication with the data line means and the sequencer means and responsive to the scan sequence signals, for controlling the selective connection of the data line means to the data locations identified by the scan sequence signals; and control logic, in communication with the sequencer means and connected to the first input-output terminal for receiving control input signals and to the second input-output terminal for receiving the scan clock signal, for controlling the sequencer means.
Claim 3
Dependent Claim
254 words
In an integrated circuit having a normal function performing sequential logic, data locations having connections for use in execution of the normal function and a plurality of input-output terminals coupled to the circuit, an apparatus for scanning the contents of the data locations independent of the connections for use in execution of the normal function comprising: data line means, in communication with a first of the input-output terminals and the data locations, for selectively connecting the data locations to the first input-output terminal across connections separate from the connections for use in execution of the normal function; sequencer means for generating scan sequence signals identifying data locations to be scanned; decoder means, in communication with the data line means and the sequencer means and responsive to the scan sequence signals, for controlling the selective connection of the data line means to the data locations identified by the scan sequence signals; and control logic, in communication with the sequencer means, for controlling the sequencer means; wherein each of the data locations comprises: a sample and hold latch circuit, the connections for use in execution of the normal function including data-in and data-out lines, a clock sample input line, and a clock hold input line; the sample and hold latch circuit further including row and column input lines, connected to receive signals from the decoder means, for accessing the latch circuit; and a scan-out gate connected to the data line means enabled by said row and column input lines, providing a scan-out of the latch circuit.
Claim 4
Dependent Claim
254 words
In an integrated circuit having a normal function performing sequential logic, data locations having connections for use in execution of the normal function and a plurality of input-output terminals coupled to the circuit, an apparatus for scanning the contents of the data locations independent of the connections for use in execution of the normal function comprising: data line means, in communication with a first of the input-output terminals and the data locations, for selectively connecting the data locations to the first input-output terminal across connections separate from the connections for use in execution of the normal function; sequencer means for generating scan sequence signals identifying data locations to be scanned; decoder means, in communication with the data line means and the sequencer means and responsive to the scan sequence signals, for controlling the selective connection of the data line means to the data locations identified by the scan sequence signals; and control logic, in communication with the sequencer means, for controlling the sequencer means; wherein each of the data locations comprises: a sample and hold latch circuit, the connections for use in execution of the normal function including data-in and data-out lines, a clock sample input line, and a clock hold input line; the sample and hold latch circuit further including row and column input lines, connected to receive signals from the decoder means, for accessing the latch circuit; and a scan-out gate connected to the data line means enabled by said row and column input lines, providing a scan-out of the latch circuit.
Claim 5
Dependent Claim
32 words
The scan apparatus of claim 2, wherein the latch circuit further includes a scan-in line for scanning in data to the latch circuit under control of said row and column input lines.
Claim 6
Dependent Claim
15 words
The scan apparatus of claim 2, wherein the latch circuit further includes a reset input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-21 | 1991-12-21 | 1992-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-21 | 1995-12-21 | 1996-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-21 | 1999-12-21 | 2000-06-21 | $7700.00 | Window Closed / Lapsed |