US4130900A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory with common read/write data line and write-in latch circuit
Assignee: Toshiba Corp
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Filing: 1977-04-25
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Granted: 1978-12-19
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Expires: 1997-04-25
Abstract
Abstract A latch circuit is provided on the input side of write-in circuit of a semiconductor memory device which is so formed that a common data line is used for data writing-in and data reading-out. Write-in data read serially into the latch circuit in a word unit is temporarily stored and held, so that the data is written simultaneously into various memory cells for in column units of the memory array.
Inventors
- 👤 Masafumi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:58
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; G11C16/06; G11C16/10; G11C8/00; G11C8/04; G11C2216/00; G11C2216/12; G11C2216/14
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
A semiconductor memory device comprising: (a) a memory array consisting of a plurality of memory cells arranged in XY matrix form, (b) an X decoder for designating the X direction address of the memory cells, (c) a Y decoder for designating the Y direction address of the memory cells, (d) a first Y direction gate circuit connected to the Y decoder and the memory array for reading out the data addressed by the X and Y decoders, (e) a read-out control circuit connected to the first Y direction gate circuit, (f) a plurality of data lines connected to the read-out control circuit for common data writing-in and data reading out, (g) a write-in circuit having a second Y direction gate circuit connected to the data lines for reading data therein in a word unit in sequence and for selecting a plurality of memory cells in sequence in accordance with Y address signals designating the memory cells, a latch circuit connected to the second Y direction gate circuit for temporarily holding data read in the gate circuit and a write-in control circuit connected to the latch circuit and the memory array for writing data held in the latch circuit into the respective memory cells selected by the second Y direction gate circuit.
Claim 2
Dependent Claim
211 words
A semiconductor memory device comprising: (a) a memory array consisting of a plurality of memory cells arranged in XY matrix form, (b) an X decoder for designating the X direction address of the memory cells, (c) a Y decoder for designating the Y direction address of the memory cells, (d) a first Y direction gate circuit connected to the Y decoder and the memory array for reading out the data addressed by the X and Y decoders, (e) a read-out control circuit connected to the first Y direction gate circuit, (f) a plurality of data lines connected to the read-out control circuit for common data writing-in and data reading out, (g) a write-in circuit having a second Y direction gate circuit connected to the data lines for reading data therein in a word unit in sequence and for selecting a plurality of memory cells in sequence in accordance with Y address signals designating the memory cells, a latch circuit connected to the second Y direction gate circuit for temporarily holding data read in the gate circuit and a write-in control circuit connected to the latch circuit and the memory array for writing data held in the latch circuit into the respective memory cells selected by the second Y direction gate circuit.
Claim 3
Dependent Claim
19 words
The semiconductor memory device according to claim 1 wherein the memory cell comprises a floating gate type MOS transistor.
Claim 4
Dependent Claim
101 words
The semiconductor memory device according to claim 2 including means for applying a control signal to the second Y direction gate circuit and a read-write signal to both the write-in control circuit and the read-out control circuit, whereby the read-write signal defines a data cycle and a program cycle of the write-in mode, in the data cycle the data in the Y direction gate circuit is written into the latch circuit in synchronization with the control signal and in the program cycle the data in the latch circuit is written into the addressed memory cells by applying a program pulse thereto.
Claim 5
Dependent Claim
35 words
The semiconductor memory device according to claim 1 wherein the memory array consists of a plurality of unit words, the data being simultaneously written into all of the memory cells arranged on an X line.
Claim 6
Dependent Claim
44 words
The semiconductor memory device according to claim 1 wherein a plurality of unit words are arranged on an X line and which is divided into a plurality of blocks, each consisting of some unit words, whereby the data is simultaneously written for each block.
Claim 7
Dependent Claim
40 words
The semiconductor memory device according to claim 4, the lower order address bits being assigned to the memory cells in the Y direction of the memory array and the higher order address bits being assigned to the X direction thereof.
References Cited (Backward Citations)
US3906461A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-18 | 1982-06-19 | 1982-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-18 | 1986-06-19 | 1986-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-18 | 1990-06-19 | 1990-12-19 | $7700.00 | Window Closed / Lapsed |