Array uniformity correction

Claim 2

A circuit for providing array uniformity correction, comprising in combination: a plurality of resistance type radiation sensor means connected in an array, each of said sensor means having an inherent electrical resistance associated therewith, the ohm magnitude of which may differ from sensor to sensor; switching means for sequentially connecting said sensor means, one at a time, to an electrical source and to a readout circuit for interrogation of said sensor means, said switching means including controllable resistance means in series with the sensor means; digital memory means storing a separate number for each of said sensor means, which numbers are a function of the inherent resistance value, respectively, of each sensor means; said memory means also providing an output of the number representing the sensor means under interrogation; and, digital-to-analog converting means connected for converting the number output of said memory means to an analog voltage and applying the analog voltage in controlling biasing relation to the controllable resistance means.

Claim 3

The circuit according to claim 1 in which each of said sensor means further includes diode means in series therewith.

Claim 4

The circuit according to claim 1 in which said switching means comprises a plurality of field effect transistors each of which is biased to a non-conductive quiescent state, and any two of which can be selectively biased to a conductive state to connect a selected corresponding sensor means for said interrogation.

Claim 5

The circuit according to claim 1 in which said controllable resistor means comprises field effect transistors.

Claim 6

A circuit for providing array uniformity correction, comprising in combination: a plurality of resistance type radiation sensor means connected in a twodimensional x-y array, each of said sensor means having an inherent electrical resistance associated therewith, the ohm magnitude of which may differ from sensor to sensor; switching means for sequentially connecting said sensor means, one at a time, to an electrical source and to a preamplifier and readout circuit for interrogation of said sensor means; digital memory means storing an individual number for each of said sensor means, which numbers are a function of the inherent resistance value, respectively, of each sensor means; said memory means also providing an output of the number representing the sensor means under interrogation; sequencer means connected to said switching means and to said memory means for synchronizing said switching means and said memory means to the sensor being interrogated; and offset correction circuit means comprising a multi-potential source connected to supply a controlled potential to said preamplifier to thereby adjust the output signal from said preamplifer to said readout circuit, said multipotential source being connected to and controlled by said memory means output.

Claim 7

A circuit for providing array uniformity correction, comprising in combination: a plurality of resistance type radiation sensor means connected in a twodimensional x-y array, each of said sensor means having an inherent electrical resistance associated therewith, the ohm magnitude of which may differ from sensor to sensor; switching means for sequentially connecting said sensor means, one at a time, to an electrical source and to a preamplifier and readout circuit for interrogation of said sensor means; digital memory means storing an individual number for each of said sensor means, which numbers are a function of the inherent resistance value, respectively, of each sensor means; said memory means also providing an output of the number representing the sensor means under interrogation; sequencer means connected to said switching means and to said memory means for synchronizing said switching means and said memory means to the sensor being interrogated; and offset correction circuit means comprising a multi-potential source connected to supply a controlled potential to said preamplifier to thereby adjust the output signal from said preamplifer to said readout circuit, said multipotential source being connected to and controlled by said memory means output.

Claim 8

The circuit according to claim 5 in which each of said sensor means further includes diode means in series therewith.

Claim 9

The circuit according to claim 5 in which said switching means comprises a plurality of field effect transistors each of which is biased to a non-conductive quiescent state, and any two of which can be selectively biased to a conductive state to connect a selected corresponding sensor means for said interrogation.

Claim 10

The circuit according to claim 5 in which said multipotential source comprises a multisection resistive voltage divider network having nodes between resistive sections and a plurality of switching means selectively connecting said nodes to a reference potential in response to a signal from said memory means.

Claim 11

The circuit according to claim 8 in which said plurality of switching means comprises in part a plurality of field effect transistors.