Patent US4751196A successfully refreshed from Google Patents.
US4751196A
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US
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High voltage thin film transistor on PLZT and method of manufacture thereof
Assignee: Motorola Solutions Inc
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Filing: 1985-04-01
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Granted: 1988-06-14
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Expires: 2005-04-01
Abstract
Abstract A high voltage thin film transistor structure and method are disclosed which make it possible to fabricate matrix displays with integrated pixel switches on PLZT substrates. A polysilicon transistor capable of withstanding more than 60 V across the source and drain and with a ratio of on to off current in excess of 10 3 is disclosed. The fabrication method disclosed is suitable for use with brittle and readily oxidizable PLZT substrates.
Inventors
- 👤 Ronald C. Pennell
- 👤 Richard D. Catero
- 👤 Stephen L. Lovelis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; G; G02; G02F; G02F1/00; G02F1/01; G02F1/03; G02F1/055; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6723; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10P; H10P10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
132 words
A method of fabricating a thin film transistor on a PLZT substrate comprising the steps of: depositing a first dielectric layer overlying said substrate; depositing a polysilicon layer overlying said first dielectric layer; defining source and drain regions in said polysilicon layer by placing a dopant therein, said source and drain regions being separated by a channel region of said polysilicon layer; depositing a second dielectric layer overlying said polysilicon; annealing said second dielectric layer in a an atmosphere that is nonoxidizing to said PLZT; depositing source and drain electrodes overlying said second dielectric layer, said source and drain electrodes penetrating said second dielectric layer to contact said source and drain regions, respectively; and depositing a gate electrode overlying said second dielectric layer and at least a portion of said channel region.
Claim 2
Independent Claim
132 words
A method of fabricating a thin film transistor on a PLZT substrate comprising the steps of: depositing a first dielectric layer overlying said substrate; depositing a polysilicon layer overlying said first dielectric layer; defining source and drain regions in said polysilicon layer by placing a dopant therein, said source and drain regions being separated by a channel region of said polysilicon layer; depositing a second dielectric layer overlying said polysilicon; annealing said second dielectric layer in a an atmosphere that is nonoxidizing to said PLZT; depositing source and drain electrodes overlying said second dielectric layer, said source and drain electrodes penetrating said second dielectric layer to contact said source and drain regions, respectively; and depositing a gate electrode overlying said second dielectric layer and at least a portion of said channel region.
Claim 3
Dependent Claim
33 words
A method according to claim 1 further comprising the steps of: placing a dopant in said channel region to a concentration in the range of 4×10 11 to 1×10 13 per square centimeter.
Claim 4
Dependent Claim
28 words
A method according to claim 1 wherein: said channel region further comprises a pair of offset regions adjacent source and drain regions and not underlying said gate electrode.
Claim 5
Dependent Claim
35 words
A method according to claim 1 wherein said step of depositing said polysilicon layer further comprises the steps of: depositing a layer of amorphous silicon; and heating said amorphous silicon to change it to polysilicon.
Claim 6
Dependent Claim
21 words
A method according to claim 1 further comprising the step of: forming a first conductive light shield underlying said polysilicon layer.
Claim 7
Dependent Claim
35 words
A method according to claim 1 further comprising the step of: depositing a passivation layer overlying said second dielectric layer and said electrodes, said passivation layer not being in a state of significant tensile stress.
References Cited (Backward Citations)
US4317686A
Cited
JPS5890782A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-14 | 1991-12-14 | 1992-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-14 | 1995-12-14 | 1996-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-14 | 1999-12-14 | 2000-06-14 | $7700.00 | Window Closed / Lapsed |