Non-inverting three state TTL logic with improved switching from a high impedance state to an active high state

Claim 2

A non-inverting three state gate having at least one input terminal, an output terminal, a first voltage terminal, a second voltage terminal, an input stage coupled between said first and second voltage terminals and to said at least one input terminals, a phase splitting stage coupled between said first and second voltage terminals, and an output stage coupled between said first and second voltage terminals and to said phase splitting stage, said output stage providing a first state output, a second state output, or a high impedance state output at said output terminal, said input stage having biasing means coupled to said phase splitting stage to inhibit said output stage from momentarily providing said second state output when said output stage is switching from said high impedance state output to said first state output.

Claim 3

An improved non-inverting three state gate having an output signal capable of assuming a first state, a second state, and a high impedance state at an output terminal, said gate coupled to receive a first input signal at a first input terminal and a second input signal at a second input terminal, both of said first and second input signals capable of assuming first or second voltage levels, including a first voltage terminal, a second voltage terminal, an output means having a first output transistor coupled between said first voltage terminal and said output terminal for supplying current to said output terminal when said first input signal has assumed said first voltage level and said second input signal has assumed said first voltage level, and a second output transistor coupled between said output terminal and said second voltage terminal for sinking current from said output terminal when said first input signal has assumed said second voltage level and said second input signal has assumed said first voltage level, said first output transistor not supplying current to said output terminal and said second output transistor not sinking current from said output terminal when said second input signal assumes said second voltage level, phase splitting means coupled to said output means for controlling said first and second output transistors including a phase splitting transistor having a collector coupled to both a base of said first output transistor and said first voltage terminal and, an emitter coupled to both a base of said second output transistor and said second voltage terminal, an input means including a PNP transistor having a base coupled to said first input terminal, an emitter coupled to said first voltage terminal and a collector coupled to said second voltage terminal, a first NPN transistor having a base coupled to an emitter of said PNP transistor, a collector coupled to said first voltage terminal, a second NPN transistor having a base coupled to the emitter of said first NPN transistor and a collector coupled to the base of said phase splitting transistor, a first diode coupled between the emitter of said second NPN transistor and said second voltage terminal, the improvement comprising: a third NPN transistor having a base coupled to a collector of said first NPN transistor and a collector coupled to said first voltage terminal; a second diode having a cathode coupled to said second input terminal and an anode coupled to the base of said third NPN transistor; and a third diode having a cathode coupled to the base of said phase splitting transistor and an anode coupled to the emitter of said third NPN transistor.

Claim 4

An improved non-inverting three state gate having an output signal capable of assuming a first state, a second state, and a high impedance state at an output terminal, said gate coupled to receive a first input signal at a first input terminal and a second input signal at a second input terminal, both of said first and second input signals capable of assuming first or second voltage levels, including a first voltage terminal, a second voltage terminal, an output means having a first output transistor coupled between said first voltage terminal and said output terminal for supplying current to said output terminal when said first input signal has assumed said first voltage level and said second input signal has assumed said first voltage level, and a second output transistor coupled between said output terminal and said second voltage terminal for sinking current from said output terminal when said first input signal has assumed said second voltage level and said second input signal has assumed said first voltage level, said first output transistor not supplying current to said output terminal and said second output transistor not sinking current from said output terminal when said second input signal assumes said second voltage level, phase splitting means coupled to said output means for controlling said first and second output transistors including a phase splitting transistor having a collector coupled to both a base of said first output transistor and said first voltage terminal and, an emitter coupled to both a base of said second output transistor and said second voltage terminal, an input means including a PNP transistor having a base coupled to said first input terminal, an emitter coupled to said first voltage terminal and a collector coupled to said second voltage terminal, a first NPN transistor having a base coupled to an emitter of said PNP transistor, a collector coupled to said first voltage terminal, a second NPN transistor having a base coupled to the emitter of said first NPN transistor and a collector coupled to the base of said phase splitting transistor, a first diode coupled between the emitter of said second NPN transistor and said second voltage terminal, the improvement comprising: a third NPN transistor having a base coupled to a collector of said first NPN transistor and a collector coupled to said first voltage terminal; a second diode having a cathode coupled to said second input terminal and an anode coupled to the base of said third NPN transistor; and a third diode having a cathode coupled to the base of said phase splitting transistor and an anode coupled to the emitter of said third NPN transistor.

Claim 5

A non-inverting three state gate capable of assuming a first state, a second state, or a high impedance state as an output signal at an output terminal, said gate coupled to receive a first input signal at a first input terminal and a second input signal at a second input terminal, both of said first and second input signals capable of assuming first or second voltage levels, comprising: output means coupled between said first and second voltage terminals, said output means including a first output transistor for supplying current to said output when said first input signal has assumed said first voltage level and said second input signal has assumed said first voltage level, and a second output transistor for sinking current from said ouput when said first input signal has assumed said second voltage level and said second input signal has assumed said first voltage level, said first output transistor not supplying current to said output and said second output transistor not sinking current from said output when said second input signal assumes said second voltage level; phase splitting means coupled between said first and second voltage terminals and coupled to said output means for controlling said first and second output transistors; and level setting means coupled between said first and second voltage terminals and coupled to said phase splitting means and responsive to said first and second input signals for substantially preventing glitches in said output when said first input signal has assumed said first voltage level and when said second input signal assumes said first voltage level.

Claim 6

A non-inverting three state gate capable of assuming a first state, a second state, or a high impedance state as an output signal at an output terminal, said gate coupled to receive a first input signal at a first input terminal and a second input signal at a second input terminal, both of said first and second input signals capable of assuming first or second voltage levels, comprising: output means coupled between said first and second voltage terminals, said output means including a first output transistor for supplying current to said output when said first input signal has assumed said first voltage level and said second input signal has assumed said first voltage level, and a second output transistor for sinking current from said ouput when said first input signal has assumed said second voltage level and said second input signal has assumed said first voltage level, said first output transistor not supplying current to said output and said second output transistor not sinking current from said output when said second input signal assumes said second voltage level; phase splitting means coupled between said first and second voltage terminals and coupled to said output means for controlling said first and second output transistors; and level setting means coupled between said first and second voltage terminals and coupled to said phase splitting means and responsive to said first and second input signals for substantially preventing glitches in said output when said first input signal has assumed said first voltage level and when said second input signal assumes said first voltage level.

Claim 7

The circuit according to claim 3 wherein said level setting means comprises: at least one first semiconductor device coupled between said first voltage terminal and said phase splitting means comprising a first current path having a first threshold, for controlling said phase splitting means; and at least one second semiconductor device coupled between said first and second voltage terminals and coupled to said phase splitting means comprising a second current path having a second threshold, said second threshold being less in value than said first threshold, said at least one second semiconductor device disabling said second current path when said first input signal assumes said first level.

Claim 8

The circuit according to claim 3 wherein said phase splitting means comprises a phase splitting transistor having a collector coupled to both said first voltage terminal and said first output transistor, an emitter coupled to both said second voltage terminal and said second output transistor, and a base coupled to said level setting means.

Claim 9

The circuit according to claim 5 wherein said level setting means comprises: a PNP transistor having a base coupled to said first input terminal, an emitter coupled to said first voltage terminal, and a collector coupled to said second voltage terminal; a first NPN transistor having a base coupled to the emitter of said PNP transistor and a collector coupled to said first voltage terminal; a second NPN transistor having a base coupled to the emitter of said first NPN transistor, a collector coupled to the base of said phase splitting transistor; a third NPN transistor having a base coupled to the collector of said first NPN transistor and a collector coupled to said first voltage terminal; a first diode having a cathode coupled to the base of said PNP transistor and an anode coupled to the base of said second NPN transistor; a second diode having a cathode coupled to the base of said phase splitter transistor and an anode coupled to the emitter of said third NPN transistor; a third diode having a cathode coupled to said second input terminal and an anode coupled to the base of said first NPN transistor; a fourth diode having a cathode coupled to said second input terminal and an anode coupled to the base of said second NPN transistor; a fifth diode having a cathode coupled to said second input terminal and an anode coupled to the base of said third NPN transistor; a sixth diode having a cathode coupled to said second input terminal and an anode coupled to the base of said phase splitting transistor; a seventh diode having a cathode coupled to said second input terminal and an anode coupled to the collector of said phase splitting transistor; and an eighth diode having a cathode coupled to said second voltage terminal and an anode coupled to the emitter of said second NPN transistor, wherein the threshold of a current path comprising said third NPN transistor, said second diode, said phase splitting transistor, and said second output transistor is larger than the threshold of a current path comprising said first NPN transistor, said second NPN transistor, and said eighth diode.