US4467223A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Enable gate for 3 state circuits
Assignee: Motorola Solutions Inc
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Filing: 1982-04-22
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Granted: 1984-08-21
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Expires: 2002-04-22
Abstract
Abstract A circuit for providing a signal which enables the high impedance state of a subsequent three state circuit includes a first circuit portion which provides current to an output node to disable the high impedance state when an input signal is in the first state and a second circuit portion which sinks current from the output node to enable the high impedance state when the input signal is in a second state. The circuit includes an input stage which is directly coupled to a transistor, which transistor simultaneously enables said second circuit portion and disables said first circuit portion when the input signal switches from said second state to said first state.
Inventors
- 👤 Eric D. Neely
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826; H03K19/0008; H03K19/001
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
195 words
A circuit for providing an enabling signal at an output thereof when an input signal is in a first state and for providing a disabling signal at said output when said input signal is in a second state, comprising: first means for supplying current to said output when said input signal is in said first state to produce said enabling signal; second means for sinking current from said output when said input signal is in said second state to produce said disabling signal; an input stage for receiving said input signal; third means coupled to said first means for enabling said first means when said input signal is in said first state and for disabling said first means and enabling said second means when said input signal is in said second state; delay means coupled between said input stage and said third means; and fourth means coupled to said second means for disabling said second means when said input signal is in said first state and for enabling said second means and disabling said first means when said input signal is in said second state, said fourth means being coupled directly to said input stage.
Claim 2
Dependent Claim
195 words
A circuit for providing an enabling signal at an output thereof when an input signal is in a first state and for providing a disabling signal at said output when said input signal is in a second state, comprising: first means for supplying current to said output when said input signal is in said first state to produce said enabling signal; second means for sinking current from said output when said input signal is in said second state to produce said disabling signal; an input stage for receiving said input signal; third means coupled to said first means for enabling said first means when said input signal is in said first state and for disabling said first means and enabling said second means when said input signal is in said second state; delay means coupled between said input stage and said third means; and fourth means coupled to said second means for disabling said second means when said input signal is in said first state and for enabling said second means and disabling said first means when said input signal is in said second state, said fourth means being coupled directly to said input stage.
Claim 3
Dependent Claim
41 words
A circuit according to claim 1 wherein said first means includes a first transistor circuit means having a collector for coupling to a source of supply voltage, a base coupled to said third means, and an emitter coupled to said output.
Claim 4
Dependent Claim
41 words
A circuit according to claim 2 wherein said second means includes second transistor circuit means having a base coupled to said fourth means, a collector coupled to said output and an emitter for coupling to a second source of supply voltage.
Claim 5
Dependent Claim
58 words
A circuit according to claim 3 wherein said third means includes third transistor circuit means having a base coupled to said delay means, a collector coupled to the base of said first transistor circuit means and for coupling to said first source of supply voltage, and an emitter coupled to the base of said second transistor circuit means.
Claim 6
Dependent Claim
48 words
A circuit according to claim 4 wherein said fourth means comprises fourth transistor circuit means having an emitter coupled to the base of said second transistor circuit means, a collector coupled to the base of said first transistor circuit means, and a base coupled to said input stage.
Claim 7
Dependent Claim
138 words
An inverter circuit having an input stage and an output, comprising: first means for supplying current to said output when said input is at a first potential; second means for sinking current from said output when said input is at a second potential; third means coupled to said first means for enabling said first means when said input is at said first potential and for disabling said first means when said input is at said second potential; delay means coupled between said input stage and said third means; and fourth means coupled to said second means for disabling said second means when said input is at said first potential and for enabling said second means and disabling said first means when said input is at said second potential, said fourth means being coupled directly to said input stage.
Claim 8
Dependent Claim
138 words
An inverter circuit having an input stage and an output, comprising: first means for supplying current to said output when said input is at a first potential; second means for sinking current from said output when said input is at a second potential; third means coupled to said first means for enabling said first means when said input is at said first potential and for disabling said first means when said input is at said second potential; delay means coupled between said input stage and said third means; and fourth means coupled to said second means for disabling said second means when said input is at said first potential and for enabling said second means and disabling said first means when said input is at said second potential, said fourth means being coupled directly to said input stage.
Claim 9
Dependent Claim
40 words
A circuit according to claim 6 wherein said first means includes first transistor circuit means having a collector for coupling to a source of supply voltage, a base coupled to said third means, and an emitter coupled to said output.
Claim 10
Dependent Claim
41 words
A circuit according to claim 7 wherein said second means includes second transistor circuit means having a base coupled to said fourth means, a collector coupled to said output and an emitter for coupling to a second source of supply voltage.
Claim 11
Dependent Claim
58 words
A circuit according to claim 8 wherein said third means includes third transistor circuit means having a base coupled to said delay means, a collector coupled to the base of said first transistor circuit means and for coupling to said first source of supply voltage, and an emitter coupled to the base of said second transistor circuit means.
Claim 12
Dependent Claim
48 words
A circuit according to claim 9 wherein said fourth means comprises fourth transistor circuit means having an emitter coupled to the base of said second transistor circuit means, a collector coupled to the base of said first transistor circuit means, and a base coupled to said input stage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-21 | 1988-02-20 | 1988-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-21 | 1992-02-20 | 1992-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-21 | 1996-02-20 | 1996-08-21 | $7700.00 | Window Closed / Lapsed |