US4743783A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse width modulator circuit for switching regulators
Assignee: National Semiconductor Corp
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Filing: 1986-08-25
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Granted: 1988-05-10
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Expires: 2006-08-25
Abstract
Abstract A circuit for pulse width modulating the output of a voltage controlled oscillator without introducing any ocillator frequency or amplitude (slope) modulation. A summing circuit is combined with a comparator and provided with inputs that accommodate differential sum/difference inputs, an error input and a ramp input from the oscillator or other source. The ramp and error signals are combined differentially to pulse width modulate the comparator output and pulse width modulation can also be achieved by via the sum/difference inputs a differential relationship.
Inventors
- 👤 Tim D. Isbell
- 👤 Walter R. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:00
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/08; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/33507; H03K3/00; H03K3/01; H03K3/017
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
283 words
A circuit for signal summing useful in pulse width modulators, said circuit comprising: first and second power supply terminals connectable to a source of operating power; a first transistor having a base coupled to a first signal voltage source, an emitter coupled to one terminal of a first scaling and linearizing resistor, and a collector coupled to one terminal of a first load element; a second transistor having a base coupled to a second voltage signal source, an emitter coupled to one terminal of a second scaling and linearizing resistor, and a collector coupled to one terminal of a second load element; means for coupling the other terminals of said first and second load elements to said first power supply terminal; means for coupling the other terminals of said first and second scaling and linearizing resistors respectively through first and second constant current devices to said second power supply terminal; a third transistor having a collector coupled to said collector of said first transistor, an emitter coupled to one terminal of a third scaling and linearizing resistor, and a base coupled to a third voltage signal source; a fourth transistor having a collector coupled to said collector of said second transistor, an emitter coupled to one terminal of a fourth scaling and linearizing resistor, and a base coupled to a fourth voltage signal source; means for coupling the other terminals of said third and fourth scaling and linearizing resistors respectively through third and fourth constant current devices to said second power supply terminal whereby said first and third voltage signal sources are summed in said first load element and said second and fourth voltage signal sources are summed in said second load element.
Claim 2
Dependent Claim
283 words
A circuit for signal summing useful in pulse width modulators, said circuit comprising: first and second power supply terminals connectable to a source of operating power; a first transistor having a base coupled to a first signal voltage source, an emitter coupled to one terminal of a first scaling and linearizing resistor, and a collector coupled to one terminal of a first load element; a second transistor having a base coupled to a second voltage signal source, an emitter coupled to one terminal of a second scaling and linearizing resistor, and a collector coupled to one terminal of a second load element; means for coupling the other terminals of said first and second load elements to said first power supply terminal; means for coupling the other terminals of said first and second scaling and linearizing resistors respectively through first and second constant current devices to said second power supply terminal; a third transistor having a collector coupled to said collector of said first transistor, an emitter coupled to one terminal of a third scaling and linearizing resistor, and a base coupled to a third voltage signal source; a fourth transistor having a collector coupled to said collector of said second transistor, an emitter coupled to one terminal of a fourth scaling and linearizing resistor, and a base coupled to a fourth voltage signal source; means for coupling the other terminals of said third and fourth scaling and linearizing resistors respectively through third and fourth constant current devices to said second power supply terminal whereby said first and third voltage signal sources are summed in said first load element and said second and fourth voltage signal sources are summed in said second load element.
Claim 3
Dependent Claim
62 words
The circuit of claim 1 further comprising: a first coupling resistor coupled between said other ends of said first and second linearizing resistors; and a second coupling resistor coupled between said other ends of said third and fourth linearizing resistors whereby said first and second voltage signal sources are combined differentially and said third and fourth voltage signal sources are combined differentially.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |