Correction circuit in television display apparatus using differential amplifiers

Claim 2

A circuit arrangement in television display apparatus for deforming a signal applied to an amplifier which applies a current to a coil for influencing the location of the landing spot of an electron beam on the screen of a television display tube, with means for applying a sawtooth input signal, the output signal undergoing an addition and/or subtraction, characterized in that the circuit arrangement includes a plurality of difference amplifiers each having a first and a second input terminal, all first input terminals being connected together and to the means for applying the input signal, the second input terminals being connected to different biasses, the difference amplifiers having a common load connected to an output terminal.

Claim 3

A circuit arrangement as claimed in claim 1, characterized in that each difference amplifier comprises a first and a second transistor and a current source in which the base electrode of the first transistor constitutes the first input terminal while the base electrode of the second transistor constitutes the second input terminal, two resistors of equal value being incorporated between the emitter electrodes of the two transistors, the current source being connected to the junction of said resistors, the collector electrode of the first transistor being connected to a terminal of a voltage supply source, the collector electrode of the second transistor being connected to the output terminal.

Claim 4

A circuit arrangement as claimed in claim 1, characterized in that each difference amplifier comprises a first and a second transistor and a current source in which the base electrode of the first transistor constitutes the first input terminal while the base electrode of the second transistor constitutes the second input terminal, two resistors of equal value being included between the emitter electrodes of the two transistors, the current source being connected to the junction of said resistors, the collector electrode of the first transistor in a number of difference amplifiers being connected to a terminal of a voltage supply source and to the collector electrode of the first transistor in the other difference amplifiers, the collector electrode of the second transistor in the former difference amplifiers being connected to the output terminal and to the collector electrode of the first transistor in the other difference amplifiers.

Claim 5

A circuit arrangement as claimed in claim 2, characterized in that each difference amplifier comprises a first and a second transistor and a current source in which the base electrode of the first transistor constitutes the first input terminal while the base electrode of the second transistor constitutes the second input terminal, two resistors of equal value being included between the emitter electrodes of the two transistors, the current source being connected to the junction of said resistors, the collector electrode of the first transistor in a number of difference amplifiers being connected to a terminal of a voltage supply source and to the collector electrode of the first transistor in the other difference amplifiers, the collector electrode of the second transistor in the former difference amplifiers being connected to the output terminal and to the collector electrode of the first transistor in the other difference amplifiers, the series arrangement of a plurality of resistors is incorporated between two direct voltage sources and that each junction of two resistors constitutes a second input terminal.

Claim 6

A circuit arrangement as claimed in claim 1, characterized in that a signal for a field output amplifier is available at the output terminal of the circuit arrangement.

Claim 7

A circuit arrangement as claimed in claim 1, characterized in that a signal for an amplifier for the dynamic convergence is available at the output terminal of the circuit arrangement.

Claim 8

A semiconductor body in which at least the difference amplifiers as claimed in claim 1 are integrated.

Claim 9

A circuit arrangement comprising means for receiving an input signal, a plurality of difference amplifiers each having a first and a second input terminal, all first input terminals being coupled together and to the means for receiving the input signal, the second input terminals comprising means for receiving respectively different biasses, an output terminal, the difference amplifiers having a common load connected to said output terminal.

Claim 10

A circuit arrangement comprising means for receiving an input signal, a plurality of difference amplifiers each having a first and a second input terminal, all first input terminals being coupled together and to the means for receiving the input signal, the second input terminals comprising means for receiving respectively different biasses, an output terminal, the difference amplifiers having a common load connected to said output terminal.