Voltage adder circuit

Claim 2

A voltage adder circuit for adding at least one signal supplied in balanced form to at least one signal supplied in unbalanced form, comprising; at least one differential transistor pair including a load coupled to collectors of each transistor of said pair, said balanced signal being supplied between bases of said transistors of said pair; and an input transistor having a base-collector coupled across at least a portion of one of said loads, said unbalanced signal being applied to an emitter of said input transistor, an output of said circuit being derived from a signal produced at the other one of said loads.

Claim 3

The voltage adder circuit of claim 1, wherein a plurality of differential transistor pairs are provided, each transistor of each of said pairs being coupled in parallel with corresponding transistors of other ones of said differential transistor pairs.

Claim 4

The voltage adder circuit of claim 2, further comprising a plurality of current sources, one of said current sources being provided for and operationally coupled to a respective one of said differential transistor pairs.

Claim 5

The voltage adder circuit of claim 1, further comprising an output transistor having a base-collector coupled across said other one of said loads, and a current source coupled in series with an emitter of said output transistor, a circuit output being taken at said emitter of said output transistor.

Claim 6

The voltage adder circuit of claim 1, further comprising a second transistor pair, each transistor of said second transistor pair having a base coupled to the collector and a collector coupled to the emitter of a corresponding one of the transistors of said differential transistor pair and an emitter coupled to an intermediate point of the corresponding load.

Claim 7

The voltage adder circuit of claim 1, further comprising a second input transistor and a second at least one differential transistor pair coupled symmetrically and complementarily with said first-mentioned input transistor and differential transistor pair.

Claim 8

An amplifier circuit having reduced distortion, comprising: an FET transistor, an input signal being applied to an input electrode of said FET transistor; a differential transistor pair comprising first and second transistors, collectors of transistors of said differential transistor pair being coupled to respective first and second loads; an input transistor having a base-collector coupled across said first load, and an emitter coupled to an output electrode of said FET transistor and to a base of said first transistor of said differential pair; an output transistor having a base-collector coupled in parallel with said second load; first through fourth current sources, said first current source supplying current to commonly connected collectors of said input transistor and said output transistors, said second current source receiving current from commonly connected emitters of said transistors of said differential transistor pair, said third current source receiving current from an emitter of said output transistor, and said fourth current source receiving current from said emitter of said input transistor; an operational amplifier having a noninverting input coupled to said emitter of said output transistor; and a resistor feedback network for providing a feedback signal to a base of said second transistor of said differential transistor pair.

Claim 9

An amplifier circuit having reduced distortion, comprising: an FET transistor, an input signal being applied to an input electrode of said FET transistor; a differential transistor pair comprising first and second transistors, collectors of transistors of said differential transistor pair being coupled to respective first and second loads; an input transistor having a base-collector coupled across said first load, and an emitter coupled to an output electrode of said FET transistor and to a base of said first transistor of said differential pair; an output transistor having a base-collector coupled in parallel with said second load; first through fourth current sources, said first current source supplying current to commonly connected collectors of said input transistor and said output transistors, said second current source receiving current from commonly connected emitters of said transistors of said differential transistor pair, said third current source receiving current from an emitter of said output transistor, and said fourth current source receiving current from said emitter of said input transistor; an operational amplifier having a noninverting input coupled to said emitter of said output transistor; and a resistor feedback network for providing a feedback signal to a base of said second transistor of said differential transistor pair.

Claim 10

The amplifier circuit of claim 7, wherein said first and second loads each comprise resistor means.

Claim 11

A voltage adder circuit for adding at lease one signal supplied in balanced form to at least one signal supplied in unbalanced form, comprising: at least one differential transistor pair including a load coupled to collectors of each transistor of said pair, said balanced signal being supplied between bases of said transistors of said pair; and an input transistor having a base-collector coupled across at least a portion of one of said loads, said unbalanced signal being applied to an emitter of said input transistor, an output of said circuit being derived from a signal produced at both of said loads, both of said loads together comprising a current mirror circuit.

Claim 12

A voltage adder circuit for adding at lease one signal supplied in balanced form to at least one signal supplied in unbalanced form, comprising: at least one differential transistor pair including a load coupled to collectors of each transistor of said pair, said balanced signal being supplied between bases of said transistors of said pair; and an input transistor having a base-collector coupled across at least a portion of one of said loads, said unbalanced signal being applied to an emitter of said input transistor, an output of said circuit being derived from a signal produced at both of said loads, both of said loads together comprising a current mirror circuit.